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Fast Digital Phase-Locked Oscillator

IP.com Disclosure Number: IPCOM000043262D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Cukier, M: AUTHOR

Abstract

The figure illustrates a fast digital phase-locked oscillator (PLO) which permits the phase of a clock signal having a frequency higher than 100 kHz to be tracked by digital circuits and which is based on the use of a delay line. The output from master oscillator 10 is fed to delay line 12 which has N taps, each being connected to one of the inputs of N AND gates A-1, A-2,...A-N, respectively. The outputs from AND gates A-1, A-2,... A-N are applied to OR gate 14 whose output drives fixed-length counter 16 which produces the phase-controlled output clock signal.

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Fast Digital Phase-Locked Oscillator

The figure illustrates a fast digital phase-locked oscillator (PLO) which permits the phase of a clock signal having a frequency higher than 100 kHz to be tracked by digital circuits and which is based on the use of a delay line. The output from master oscillator 10 is fed to delay line 12 which has N taps, each being connected to one of the inputs of N AND gates A-1, A-2,...A-N, respectively. The outputs from AND gates A-1, A-2,... A-N are applied to OR gate 14 whose output drives fixed-length counter 16 which produces the phase-controlled output clock signal. The output from counter 16 is compared with the reference clock signal to be tracked in phase comparator 18, which selectively produces a speed-up or slow-down signal depending on the phase relationship between the output clock signal and the reference clock signal, when reference clock transitions are detected. The speed-up and slow-down signals from comparator 18 control the up and down inputs, respectively, of Modulo N up-down counter 20. The count set in counter 20 selects the appropriate tap signal which is to be fed to counter 16 through decode circuit 22, AND gates A-1, A-2,...A-N, and OR gate 14. Assuming that d and T are the delay between two consecutive taps and the period of master oscillator 10, respectively, when (N + 1) x d = T, the delay line can generate N different values of the phase of the signal produced by master oscillator 10. The PLO illustrated i...