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Sidewall-Defined Self-Aligned Reach-Up Isolation

IP.com Disclosure Number: IPCOM000043265D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Wang, W: AUTHOR

Abstract

This article describes a bipolar isolation scheme in which a sidewall process is used to produce self-aligned and closely spaced subcollector and isolation diffusions prior to epi deposition. The process is shown in Figs. 1-4. The starting material is a p-type substrate 1. P+ polysilicon 2 and thick silicon dioxide or nitride 3 are deposited, patterned with standard photolithographic processes, and reactive ion etched to obtain the vertical walled structure shown in Fig. 1. A thick layer of chemical vapor deposited oxide is then deposited which tends to follow the contours of the existing structure. It is then blanket reactive ion etched until the substrate is again exposed. The directional effect of the etching leaves a sidewall of oxide 4 covering the polysilicon 2.

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Sidewall-Defined Self-Aligned Reach-Up Isolation

This article describes a bipolar isolation scheme in which a sidewall process is used to produce self-aligned and closely spaced subcollector and isolation diffusions prior to epi deposition. The process is shown in Figs. 1-4. The starting material is a p-type substrate 1. P+ polysilicon 2 and thick silicon dioxide or nitride 3 are deposited, patterned with standard photolithographic processes, and reactive ion etched to obtain the vertical walled structure shown in Fig. 1. A thick layer of chemical vapor deposited oxide is then deposited which tends to follow the contours of the existing structure. It is then blanket reactive ion etched until the substrate is again exposed. The directional effect of the etching leaves a sidewall of oxide 4 covering the polysilicon 2. The sidewall length 5 governs the spacing, as shown in Fig. 2. A thin oxide layer 6 may be left in the hollows or is grown before implant 7. Then, an N-type impurity, such as arsenic, is implanted in the exposed substrate to form an n+ region 7. The thick oxide around the p+ region protects it from implantation. This is the self-aligning feature. The wafers are then put through a drive-in process, and the oxide 4 is then etched away. After going through N-type epi growth 8 and a recessed oxide isolation process 9, the final isolation structure is as shown in Fig. 4.

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