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One-Mask Method for Realizing Self-Aligned Subcollectors and Subisolations in Bipolar Processes

IP.com Disclosure Number: IPCOM000043269D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 95K

Publishing Venue

IBM

Related People

Jambotkar, CG: AUTHOR [+2]

Abstract

A method is described for realizing self-alignment between subcollector and subisolation regions in bipolar processes. This method requires only one masking operation and, at the same time, it provides a separation between the self-aligned subcollector and subisolation windows. The windows can be as large as necessary, for example, from about 1 mm to 4 mm. It is important to recognize that in high-performance products the subcollector and the subisolation must be kept sufficiently away from each other to keep collector-substrate capacitance low. Since self- alignment of subcollector and subisolation allows reduction in the subcollector-to-subisolation spacing by about 1 mm on each one of the four sides of a subcollector, significant improvement in chip density becomes possible. The outline of this method is as follows: 1.

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One-Mask Method for Realizing Self-Aligned Subcollectors and SubIsolations in Bipolar Processes

A method is described for realizing self-alignment between subcollector and subisolation regions in bipolar processes. This method requires only one masking operation and, at the same time, it provides a separation between the self-aligned subcollector and subisolation windows. The windows can be as large as necessary, for example, from about 1 mm to 4 mm. It is important to recognize that in high-performance products the subcollector and the subisolation must be kept sufficiently away from each other to keep collector- substrate capacitance low. Since self- alignment of subcollector and subisolation allows reduction in the subcollector-to-subisolation spacing by about 1 mm on each one of the four sides of a subcollector, significant improvement in chip density becomes possible. The outline of this method is as follows: 1. Starting with P- substrate 2, form SiO2 layer 4, Si3N4 layer 6, SiO2 layer 8, Si3N4 layer 10, SiO2 layer 12 and Si3N4 layer 14 successively one above another. Then using a mask, reactive ion etch (RIE) subcollector windows in the entire stack of SiO2-Si3N4 layers. Preferably, form a thin screen SiO2 layer 16 over the exposed silicon and implant ions of N dopant 18, for example, arsenic, into the silicon under the screen oxide, as illustrated in Fig. 1. 2. After a suitable annealing heat cycle, using selective wet or plasma etching, form undercuts of about 1 mm in SiO2 layers 4, 8 and 12, as illustrated at 20 in Fig. 2. Buffered HF is a typical wet etchant which may be used. 3. Now, using selective wet (or plasma) etching, again form undercuts 22 of about 1 mm in Si3N4 layers 6 and 10 relative to the SiO2 edges, as illustrated in Fig. 3. The top Si3N4 layer 12 gets removed during this etching. Hot H3PO4 is...