Browse Prior Art Database

I2L CELL WITH MULTIPLE TOP COLLECTORS (EMITTERS OF INVERSELY OPERATED NPNs)

IP.com Disclosure Number: IPCOM000043283D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Wong, RC: AUTHOR

Abstract

Fig. 1 shows the circuit diagram of an I2L memory cell. This cell can be integrated into a small area and requires low power. However, because the bit lines are used for both injector bias and sensing, read access time is relatively long. Also, the sense voltage is limited in magnitude, and hence relatively sophisticated support circuits are required. The I2L memory cell of Fig. 2 is herein proposed. This cell differs from the cell of Fig. 1 in that: (1) an additional top collector contact is required for each of the transistors T1 and T2, and (2) an additional "word line" is required. Further, in the cell of Fig. 2 a single PNP transistor can be shared by two cells. The operation of the cell of Fig. 2 is illustrated in Fig. 3, where an arbitrary set of voltage levels is set forth.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 67% of the total text.

Page 1 of 2

I2L CELL WITH MULTIPLE TOP COLLECTORS (EMITTERS OF INVERSELY OPERATED NPNs)

Fig. 1 shows the circuit diagram of an I2L memory cell. This cell can be integrated into a small area and requires low power. However, because the bit lines are used for both injector bias and sensing, read access time is relatively long. Also, the sense voltage is limited in magnitude, and hence relatively sophisticated support circuits are required. The I2L memory cell of Fig. 2 is herein proposed. This cell differs from the cell of Fig. 1 in that:
(1) an additional top collector contact is required for each of the transistors T1 and T2, and (2) an additional "word line" is required.

Further, in the cell of Fig. 2 a single PNP transistor can be shared by two cells. The operation of the cell of Fig. 2 is illustrated in Fig. 3, where an arbitrary set of voltage levels is set forth. The standby operations and cell stability requirements are depicted by the cell connected to the second from the left pair of bit lines.

The extra bases-collectors of T1 and T2 are back-biased and have little effect on the cell. For read, the bit lines are floated and the selected lines, WL and DL, are raised. A voltage difference of about 0.6 V. will develop across BL0 and BL1. For write, the bit lines are set to 1.2 V. and 1.8 V. The word line (WL) and drain line (DL) are raised. While the high node of the cell is clamped by the bit line, the injected charge will accumulate on the base of the NPN on the other...