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Memory Cycle Interleave on a Microprocessor With Dedicated Bus

IP.com Disclosure Number: IPCOM000043290D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Dillinger, JR: AUTHOR [+2]

Abstract

A microprocessor that has a dedicated bus and no memory sharing capability, which may be, for instance, the INTEL 8051, is enhanced in its performance by adding direct memory access capability. To that end, an external direct memory access (DMA) feature is added to synchronize memory bus cycles to the microprocessor and prioritize the bus requests. The 8051 requires its memory bus only during the times that its read or write signal is active. As shown in Fig. 1, the 8051 read and write signals are active for only six 8051 clock periods out of a 12- clock cycle. The bus is then available for DMA use during the six clock periods unused in an 8051 read or write cycle. The bus is available for DMA use during all 12 clock periods in an 8051 cycle not requiring a memory access.

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Memory Cycle Interleave on a Microprocessor With Dedicated Bus

A microprocessor that has a dedicated bus and no memory sharing capability, which may be, for instance, the INTEL 8051, is enhanced in its performance by adding direct memory access capability. To that end, an external direct memory access (DMA) feature is added to synchronize memory bus cycles to the microprocessor and prioritize the bus requests. The 8051 requires its memory bus only during the times that its read or write signal is active. As shown in Fig. 1, the 8051 read and write signals are active for only six 8051 clock periods out of a 12- clock cycle. The bus is then available for DMA use during the six clock periods unused in an 8051 read or write cycle. The bus is available for DMA use during all 12 clock periods in an 8051 cycle not requiring a memory access. Since I/O adapters and the memory used can latch data within four clock periods, optimum response is achieved by implementing a bus cycle of four clock periods and allocating one bus cycle per DMA request or 8051 write request and two bus cycles per 8051 read request, as depicted in the last line of Fig. 1. A gray code counter shown in Fig. 2 counts four clock periods per bus cycle with the Z-1 count synchronized to the 8051 read or write signal. The Z-1 count is then used to interleave DMA cycles with 8051 read and write cycles, as shown in the last line of Fig. 1. Fig. 2 shows the circuitry that synchronizes bus cycles to the 8051,...