Browse Prior Art Database

Method for Digital Dual-Channel Direction Sensing

IP.com Disclosure Number: IPCOM000043294D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Polk, DR: AUTHOR [+2]

Abstract

This article describes a low-cost means of sensing direction in DC servo motors when using a dual-channel sensor having digital, quadrature outputs. This design (Figs. 1, 2, and 3) provides an efficient means for sensing direction by recognizing that it is necessary to store in memory only one previous output state (AL) of the two-channel emitter. With this information, plus recognition of the current state of each channel, the direction can be logically sensed on each transition of the emitters (A and B in the illustrations). The desired Boolean function is represented in Fig. 1. It will be noted that AL represents the previous state of emitter A. A timing diagram of left and right direction is presented in Fig. 2.

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Method for Digital Dual-Channel Direction Sensing

This article describes a low-cost means of sensing direction in DC servo motors when using a dual-channel sensor having digital, quadrature outputs. This design (Figs. 1, 2, and 3) provides an efficient means for sensing direction by recognizing that it is necessary to store in memory only one previous output state (AL) of the two-channel emitter. With this information, plus recognition of the current state of each channel, the direction can be logically sensed on each transition of the emitters (A and B in the illustrations). The desired Boolean function is represented in Fig. 1. It will be noted that AL represents the previous state of emitter A. A timing diagram of left and right direction is presented in Fig.
2. In this diagram, CLK-L indicates the point at which the output is latched, while DD-S denotes the point at which the clock latch will sample a typical pulse. Fig. 3 illustrates the logic circuit which implements this basic concept. Clock pulses are generated upon every emitter transition. Modules B-l-A and B-l-B are buffers, while C-l and C-2 are latches. Module B-4 comprises a data selector which implements the Boolean function. Module C-l stores the previous state of emitter
A. Module B-3 provides delay to ensure that the desired signal (DD) does not change until the positive transition of the clock signal latches the output (at latch C-2).

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