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Direct DMA Tester Control and Data Transfer

IP.com Disclosure Number: IPCOM000043305D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Cha, CW: AUTHOR [+3]

Abstract

Microprocessor control or tight coupling of a microprocessor with tester hardware is avoided by the use of the present technique which restructures tester hardware and functional test data such that the tester is driven directly with minimum microprocessor support. The tester hardware is designed to utilize minimum data volume without functional restrictions. Additionally, the system data transfer time is minimized due to decreased data volume. Previous logic test (LT) systems utilize the Direct Memory Access (DMA) storage as a buffer for the 0/1 patterns to be applied to a product under test via the tester hardware. The DMA and tester hardware are, in turn, controlled by the microprocessor.

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Direct DMA Tester Control and Data Transfer

Microprocessor control or tight coupling of a microprocessor with tester hardware is avoided by the use of the present technique which restructures tester hardware and functional test data such that the tester is driven directly with minimum microprocessor support. The tester hardware is designed to utilize minimum data volume without functional restrictions. Additionally, the system data transfer time is minimized due to decreased data volume. Previous logic test (LT) systems utilize the Direct Memory Access (DMA) storage as a buffer for the 0/1 patterns to be applied to a product under test via the tester hardware. The DMA and tester hardware are, in turn, controlled by the microprocessor. In order to apply a string of patterns to the Device Under Test (DUT), the microprocessor must decode and execute a routine (op-code) consisting of multiple instructions per function. Some of these instructions are used to set up the DMA, and others to control the tester hardware via the microprocessor. The previous test data format, shown in Fig. 1, consists of a functional sequence record (FSR) and an associated functional pattern record (FPR). The FSR is loaded in the DMA and accessed by the tester hardware during execution. The FPR consists of a 0/1 string of patterns only. The new concept (Fig. 2) restructures the FSR and FPR by concatenating the function contained in the FSR op-code to the pattern data string and thereby elimi...