Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Imbedded Decoupling Capacitors for the Transverse Via Module

IP.com Disclosure Number: IPCOM000043309D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 64K

Publishing Venue

IBM

Related People

Crowder, G: AUTHOR [+2]

Abstract

A transverse via module utilizes about 25% of it's ceramic layers, the rest being blanks serving as space holders (Fig. 1A). layer thicknesses can be varied considerably as long as a layer boundary exists at every 25.4 mm (100-mils) increment for the pins., The scheme addressed by this article envisages the elimination of existing discrete card or module chip circuit decoupling capacitors and their incorporation into previously unused areas on the transverse via modules. It further provides for an integrated approach where the capacitor is formed as part of the substrate. As shown in Fig. 1B, the best location for embedding such decoupling capacitors would be in both ends of the substrate and in the area directly below the chip.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 80% of the total text.

Page 1 of 2

Imbedded Decoupling Capacitors for the Transverse Via Module

A transverse via module utilizes about 25% of it's ceramic layers, the rest being blanks serving as space holders (Fig. 1A). layer thicknesses can be varied considerably as long as a layer boundary exists at every 25.4 mm (100-mils) increment for the pins., The scheme addressed by this article envisages the elimination of existing discrete card or module chip circuit decoupling capacitors and their incorporation into previously unused areas on the transverse via modules. It further provides for an integrated approach where the capacitor is formed as part of the substrate. As shown in Fig. 1B, the best location for embedding such decoupling capacitors would be in both ends of the substrate and in the area directly below the chip. A section of the MLC structure is made up of many layers of high dielectric material which would provide a high value decoupling capacitor. Since these layers can be placed directly below the chip, a low inductance path between chip and decoupling capacitor is also provided. As shown in Fig. 1C, the proposed capacitor, two rows of pins would be used as the decoupling capacitor leads, thereby giving the capacitor far less lead inductance than available by conventional means. Effective lead inductances of less than
0.2 nH are expected, to the power plane, resulting in improved switching limits for any LSI and VLSI circuitry employed in future system programs. Fig. 1D provides an e...