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Automatic Synthesis of Worst-Case Compensation Networks for Power Converters

IP.com Disclosure Number: IPCOM000043312D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Lleonart, G: AUTHOR

Abstract

This article describes the development of an algorithm to be used in the design of compensation networks for regulated DC-to-DC power converters. Taken into account are component tolerances and the effect of limited amplifier gain and bandwidth. The algorithm is designed to be suitable for implementation with commercial pulse-width modulation type converters. The compensation network, as shown in Fig. 1, is used to stabilize the loop. This is done by introducing a pole at a very low frequency, two zeros to cancel the effect of the pair of complex poles of the LC filter, and one pole to cancel the effect of the zero introduced by the equivalent series resistance (ESR) of the filter capacitor, as shown in Fig. 2.

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Automatic Synthesis of Worst-Case Compensation Networks for Power Converters

This article describes the development of an algorithm to be used in the design of compensation networks for regulated DC-to-DC power converters. Taken into account are component tolerances and the effect of limited amplifier gain and bandwidth. The algorithm is designed to be suitable for implementation with commercial pulse-width modulation type converters. The compensation network, as shown in Fig. 1, is used to stabilize the loop. This is done by introducing a pole at a very low frequency, two zeros to cancel the effect of the pair of complex poles of the LC filter, and one pole to cancel the effect of the zero introduced by the equivalent series resistance (ESR) of the filter capacitor, as shown in Fig. 2. The algorithm chooses the values of the components in the compensation network and verifies that the desired criteria is obtained under worst-case conditions. In calculating worst-case conditions, the effect of the filter component tolerances is taken into account. The flow diagram of Fig. 3 shows the algorithm steps to obtain a Bode plot of the analysis for worst-case specifications. The inputs to the program are as follows: 1. Desired relative stability criteria (Phase Margin (PM), Gain Margin (GM), and Minimum Phase); 2. Input voltage, transformer turns ratio and sawtooth or modulator voltage; 3. Output filter components and their tolerances including, L, C, ESR and filter damp...