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Method for Improving Cascode Switch Chip Design

IP.com Disclosure Number: IPCOM000043317D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 5 page(s) / 63K

Publishing Venue

IBM

Related People

Hauge, PS: AUTHOR [+2]

Abstract

This publication relates generally to automated VLSI circuit design, and more specifically to improving the design of cascode logic as implemented in current switch and voltage switch tree circuits. The improvement increases chip wirability and provides a convenient method for correcting associated timing problems. More particularly, techniques are described to obtain better solutions to the design problems of wiring and timing. The techniques are based on the fact that a particular Boolean expression may be implemented in any of several tree structures (topologies). In general, these structures differ as to number of transistors, as to which branch or which level of the tree contains a particular variable, and as to how efficiently (wire length, vias) the transistors can be connected within the tree.

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Method for Improving Cascode Switch Chip Design

This publication relates generally to automated VLSI circuit design, and more specifically to improving the design of cascode logic as implemented in current switch and voltage switch tree circuits. The improvement increases chip wirability and provides a convenient method for correcting associated timing problems. More particularly, techniques are described to obtain better solutions to the design problems of wiring and timing. The techniques are based on the fact that a particular Boolean expression may be implemented in any of several tree structures (topologies). In general, these structures differ as to number of transistors, as to which branch or which level of the tree contains a particular variable, and as to how efficiently (wire length, vias) the transistors can be connected within the tree. Within a given chip design, one of the tree structures will be preferred: because it is compact (fewest transistors), because it is easily connected to neighboring trees, because it provides a quick path through the tree for an almost-late signal, or because it is "porous" with respect to global wires.

Present design tools select from among the possible trees before it is known which of these considerations is the most important. As a consequence, placement and wiring programs must deal with pieces of circuitry which have been given a highly preferred internal placement (by virtue of prespecifying their internal connectivity) without regard to their surroundings. The techniques described herein keep track, at tree generation time, of all tree structures appropriate to a given Boolean expression which are likely to be preferred in a particular environment. Thus, while one tree is selected initially on its own merits, we permit it to be replaced later by a functionally equivalent tree which is better suited to its local environment. The suitability is determined by considerations encountered in the logical (timing, critical delay paths) and physical (placement, wiring) design stages. Fig. 1 compares the proposed method (double arrows) with the method in current use (single arrows). At present, cascode switch logic design begins with a high-level description of the logic. It is then transformed by manipulation of the logical expressions into a set of trees, each of which can be described by a Boolean function of several variables. The logic is minimized, and, by finding common subexpressions, is decomposed into optimal tree circuits for the desired target technology. The height of the trees is typically limited to a specified maximum value. In the new technique described herein, certain information about each Boolean expression is collected before a particular tree is chosen to represent it that is, before the variables are assigned to levels and before the variable connectivity (sequencing) is defined. Table I below shows a set of simple Boolean expressions after local decomposition into...