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Logic Design for a Shift Register Latch to Support AC Self-Testing of LSSD Circuitry

IP.com Disclosure Number: IPCOM000043322D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 4 page(s) / 65K

Publishing Venue

IBM

Related People

Barzilai, Z: AUTHOR [+2]

Abstract

The Shift Register Latch (SRL) shown in Fig. 1 supports an AC self- testing procedure when a level control signal is held to an appropriate value and clock pulses are supplied in the relationships shown in Fig. 2. Details and variants follow. The inputs to the SRL, shown in Fig. 1, are a level control signal (shown entering from the left), four clock signals (shown entering from above), and two values to be latched (shown entering from below). The system value is generated along functional paths. The scan value is generated at the +L2 output of another SRL or at an input pin for the device containing the SRL. As in LSSD circuitry [3], the SRLs are to be grouped in scan chains with the following properties. First, the same clocks go to all SRLs in the chain.

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Logic Design for a Shift Register Latch to Support AC Self-Testing of LSSD Circuitry

The Shift Register Latch (SRL) shown in Fig. 1 supports an AC self- testing procedure when a level control signal is held to an appropriate value and clock pulses are supplied in the relationships shown in Fig. 2. Details and variants follow. The inputs to the SRL, shown in Fig. 1, are a level control signal (shown entering from the left), four clock signals (shown entering from above), and two values to be latched (shown entering from below). The system value is generated along functional paths. The scan value is generated at the +L2 output of another SRL or at an input pin for the device containing the SRL. As in LSSD circuitry [3], the SRLs are to be grouped in scan chains with the following properties. First, the same clocks go to all SRLs in the chain. Second, the chain is linked by taking the scan value input to each SRL from the +L2 output of the next SRL (until the chain ends at an input pin). Third, each SRL acts as one latch for system purposes. The outputs +L1 and -L1 of the L1 latch may feed system data paths, or the outputs +L2 and -L2 of the L2 latch may feed system data paths. No SRL feeds system data paths from both L1 and L2. (This condition is violated in a recent extension of LSSD [2].) As in the BILBO proposal for DC self-test[4], the same level control signals go to all SRLs in the chain. The logical functions presupposed in the SRL are as follows. When the clock governing the polarity-hold latch L2 is down, the +L2 output has a constant binary value and the -L2 output has the negation of this value. When the governing clock is up and the input signal remains at a binary value V for a length of time comparable to the pulse width of the clock, the +L2 output becomes V and the -L2 output becomes the negation of V. The latch L1 is similar but is governed by three clocks. There are three input signals, one for each clock. (A variant with only the usual two clocks will be considered later.) The other devices in Fig. 1 are logic gates with the functions AND (gate G1) and XOR (gate G2). For AC self-testing, the clocking scheme is as shown in Fig. 2. The procedure for AC self-testing is as follows. One scan chain is temporarily designated "input" and another is temporarily designated "output" in order to test the combinational logic fed by the input chain and feeding the output chain. The input chain is put into scan mode by holding the test switch level control signal down. The output chain is put into test mode by holding it up. Clocks A, B, F are supplied to the input chain. During each pulse of the A clock, a new pseudo-random bit enters the input chain and the old bits are shifted along the chain. During each pulse of the F clock, the bits currently in the input chain are negated without shifting. (The F clock is so named because it controls this flipping of latches.) Only the A and B clocks are supplied to the output chain. It s...