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Engineering Change Method for MLC Modules

IP.com Disclosure Number: IPCOM000043328D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 23K

Publishing Venue

IBM

Related People

Kraus, CJ: AUTHOR [+3]

Abstract

This article describes a technique and structure for eliminating the need for top surface engineering change (EC) pads on multilayer ceramic (MLC) modules by using discretionary EC wiring planes. A variable number of these discretionary EC wiring planes 1 are placed between the conventional redistribution planes 3 and the personality plane pairs 5. When engineering changes are required, it is only necessary to redesign the EC wiring planes. For example, to change the net from chip pad B to chip pad A, vias 7 are omitted, isolating circuit line 9 and chip pad B. New vias 11 are punched and a new line 13 is run on the EC plane, connecting chip pad A to the circuit. This technique allows greater top surface chip density and permits engineering changes to be made without redesigning all of the personality layers.

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Engineering Change Method for MLC Modules

This article describes a technique and structure for eliminating the need for top surface engineering change (EC) pads on multilayer ceramic (MLC) modules by using discretionary EC wiring planes. A variable number of these discretionary EC wiring planes 1 are placed between the conventional redistribution planes 3 and the personality plane pairs 5. When engineering changes are required, it is only necessary to redesign the EC wiring planes. For example, to change the net from chip pad B to chip pad A, vias 7 are omitted, isolating circuit line 9 and chip pad B. New vias 11 are punched and a new line 13 is run on the EC plane, connecting chip pad A to the circuit. This technique allows greater top surface chip density and permits engineering changes to be made without redesigning all of the personality layers.

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