Browse Prior Art Database

Buried Storage Capacitor Dynamic RAM Cell

IP.com Disclosure Number: IPCOM000043332D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Kotecha, H: AUTHOR

Abstract

Single-device, FET dynamic memory cells are found in the prior art, for example, in U.S. Patent 3,387,286. These dynamic memory cells typically consist of a single FET device and a charge storage capacitor which are serially connected between a bit line and a reference potential. The FET device has its gate connected to a word line so that binary charge states may be selectively transmitted from the bit line through the transistor to the charge storage capacitor by selectively pulsing the word line. One problem associated with prior-art FET dynamic memory devices is the relatively large surface area occupied by the charge storage capacitor. The invention disclosed herein provides one solution to this problem.

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Buried Storage Capacitor Dynamic RAM Cell

Single-device, FET dynamic memory cells are found in the prior art, for example, in U.S. Patent 3,387,286. These dynamic memory cells typically consist of a single FET device and a charge storage capacitor which are serially connected between a bit line and a reference potential. The FET device has its gate connected to a word line so that binary charge states may be selectively transmitted from the bit line through the transistor to the charge storage capacitor by selectively pulsing the word line. One problem associated with prior-art FET dynamic memory devices is the relatively large surface area occupied by the charge storage capacitor. The invention disclosed herein provides one solution to this problem. The figure shows a cross-sectional view of the structure of a semiconductor arrangement for embodying the FET charge transfer device 1 and the charge storage capacitor 2 so that the charge storage capacitor lies beneath the FET transfer device. A P+ doped silicon substrate 3, having a P- type epitaxial layer 5 deposited thereon, surrounds an N+ type subcollector region 4. The PN junction formed between the Ntype region 4 and the epitaxial layer 5 and semiconductor substrate 3 serves as the charge storage capacitor 2 for the single-device dynamic RAM cell. The FET transfer device 1 is formed above the charge storage capacitor 2 by forming an N-type reach through region 6 in the epitaxial layer 5 and out-diffusing the N-type region 6 so that it makes electrical contact with the buried N-type subcollector region 4. Then, in order to form an N channel FET device 1, an N-type drai...