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T3L Logic Circuit Family

IP.com Disclosure Number: IPCOM000043335D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Boudon, G: AUTHOR

Abstract

The T3L logic circuit family consists of TTL circuits wherein a double transistor has been added to improve the logic capability of the TTL logic family. The basic T3L circuit is shown in Fig. 1. It comprises double transistor T4, T5 which allows the NAND function of inputs A and B and the AND function of inputs C and D to be performed. Inputs C and D have a threshold which is 200 mV higher than the A and B TTL inputs, and thus are less sensitive to the noise so that these inputs can be connected on long nets on a chip. Based on this basic T3L circuit, the 9 transistors of the cell shown in Fig. 2 may be wired to build various logic circuits. An exclusive-OR circuit is shown in Fig. 3. The cell can also be divided into two independent 3-input NANDs to be used as a two-way multiplexer, as shown in Fig. 4. Fig.

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T3L Logic Circuit Family

The T3L logic circuit family consists of TTL circuits wherein a double transistor has been added to improve the logic capability of the TTL logic family. The basic T3L circuit is shown in Fig. 1. It comprises double transistor T4, T5 which allows the NAND function of inputs A and B and the AND function of inputs C and D to be performed. Inputs C and D have a threshold which is 200 mV higher than the A and B TTL inputs, and thus are less sensitive to the noise so that these inputs can be connected on long nets on a chip. Based on this basic T3L circuit, the 9 transistors of the cell shown in Fig. 2 may be wired to build various logic circuits. An exclusive-OR circuit is shown in Fig. 3. The cell can also be divided into two independent 3-input NANDs to be used as a two-way multiplexer, as shown in Fig. 4. Fig. 5 shows a hazard-free polarity-hold latch which can be used as the L2 latch in the shift register latch (SRL) used in the level sensitive scan design (LSSD) concept. In this latch transistor T4 is connected to a DATA input to allow a hazard-free operation during a down-going transition of the clock input. Fig. 6 shows the L1 latch of the SRL which is less complex than the L2 latch (Fig 5). To operate, this latch one needs an additional clock input, which provides the NOR function of all clocks coupled to each data input.

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