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Voltage-Controlled Oscillator Drift Detector

IP.com Disclosure Number: IPCOM000043337D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Wicker, CR: AUTHOR

Abstract

A first-in, first-out (FIFO) buffer is used to determine when a voltage-controlled oscillator (VCO) in a data terminal equipment (DTE) is running either too slowly or too fast with respect to a single reference clock which is used to provide clocking signals for a ring communication network. In such networks a single clock is used to clock the ring and all other stations thereon using a VCO to receive and transmit data. A problem arises when the station clocking the ring becomes disabled and, as a result, no longer provides the clocking. The VCO in each station may drift outside its lock range because a ring with no clocking station creates a feedback path. All stations are transmitting using the VCO while at the same time trying to stay phase-locked to their receive data.

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Voltage-Controlled Oscillator Drift Detector

A first-in, first-out (FIFO) buffer is used to determine when a voltage-controlled oscillator (VCO) in a data terminal equipment (DTE) is running either too slowly or too fast with respect to a single reference clock which is used to provide clocking signals for a ring communication network. In such networks a single clock is used to clock the ring and all other stations thereon using a VCO to receive and transmit data. A problem arises when the station clocking the ring becomes disabled and, as a result, no longer provides the clocking. The VCO in each station may drift outside its lock range because a ring with no clocking station creates a feedback path. All stations are transmitting using the VCO while at the same time trying to stay phase-locked to their receive data. The problem can be alleviated by designing each station on the ring to have the capability of being the clocking station. Thus, in the event that the single clocking station is lost, a secondary station resumes the clocking function and removes the jitter from the ring. The figure shows one implementation for designing the jitter removal function into ring stations. The jitter is removed by a FIFO buffer, also called a dribble-down buffer. The FIFO buffer is written by the VCO clock and read by the ring clock. The FIFO buffer has the capability of detecting overrun (FIFO buffer full and a write request) and underrun (FIFO buffer empty and a read requ...