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Pipelining CZ Latches and Local Store Updating

IP.com Disclosure Number: IPCOM000043341D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 13K

Publishing Venue

IBM

Related People

Lechaczynski, M: AUTHOR [+4]

Abstract

In order to maintain the high performance level of a processor (i.e., at a short cycle) when implementing the parity generation/checking and the zero detection on the arithmetic and logical unit (ALU) output, the carry zero (CZ) latch updating and the local store updating, these operations are pipelined and performed during the cycle following the ALU operations. The longest path delay must be used when defining the cycle time of a processor. Usually this longest path includes the ALU. In addition to the ALU operation and behind it, the following additional operations have to be performed in this logic path: . parity generation and checking, zero detection, CZ latch updating. . local store updating.

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Pipelining CZ Latches and Local Store Updating

In order to maintain the high performance level of a processor
(i.e., at a short cycle) when implementing the parity generation/checking and the zero detection on the arithmetic and logical unit (ALU) output, the carry zero (CZ) latch updating and the local store updating, these operations are pipelined and performed during the cycle following the ALU operations. The longest path delay must be used when defining the cycle time of a processor. Usually this longest path includes the ALU. In addition to the ALU operation and behind it, the following additional operations have to be performed in this logic path: . parity generation and checking, zero detection, CZ latch updating. . local store updating. Performing all these operations in the ALU path results in a long processor cycle, therefore, they are performed during a second cycle. CZ latches are indicators modified by instructions and made available any time to the control program which can perform conditional branches based on their values. These latches are modified by the instruction according to: . a read only storage (ROS) picocode field specifying the test to be done.

. the carry bits from the result bytes

. the parity bits associated with result bytes

. the zero detect on the result bytes. CZ latch updating is not performed during the cycle of the ALU operation but during the following cycle. At the end of the ALU operation, the result is latched in a Z register, but no parity checking/ generation, no zero detection, and no CZ updating have been performed. The ROS picocode CZ field has been latched in a CNC (control for ne...