Browse Prior Art Database

Fault/Event Decoder

IP.com Disclosure Number: IPCOM000043353D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Sears, KH: AUTHOR

Abstract

The Fault/Event Decoder circuit, which can be used to monitor events or fault conditions that occur randomly, can store the event in memory or on a display and be reset to detect the next event in time. The fault condition F1 to Fn in Fig. 1 is enabled by the " - ANY FAULT" signal on line 11 and allowed through to the D input of the flip-flop. The fault will also generate the clock through the OR gate 12 to latch up the fault for the display or memory read. The delay of the OR gate must allow enough time for the set up of the flip-flop. The NOR gate 13 will generate a " - ANY FAULT" signal which will block out other faults from being detected because they may have been caused by the original fault. The signal can also be used to shut a system down for protection.

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Fault/Event Decoder

The Fault/Event Decoder circuit, which can be used to monitor events or fault conditions that occur randomly, can store the event in memory or on a display and be reset to detect the next event in time. The fault condition F1 to Fn in Fig. 1 is enabled by the " - ANY FAULT" signal on line 11 and allowed through to the D input of the flip-flop. The fault will also generate the clock through the OR gate 12 to latch up the fault for the display or memory read. The delay of the OR gate must allow enough time for the set up of the flip-flop. The NOR gate 13 will generate a " - ANY FAULT" signal which will block out other faults from being detected because they may have been caused by the original fault. The signal can also be used to shut a system down for protection. A clear signal 14 will reset the fault decoder which will wait for the next fault. The n-line BCD encoder 15 can be designed to detect simultaneous faults if this is a concern. Fig. 2 and Fig. 3 show an implementation of the Fault/Event De coder. PS 1 to PS 4 are power supplies. The voltage comparators (VC) are the fault detectors and input the faults into the AND gates. The fault is then latched in the D flip-flop (74LS147) which then converts the fault into a binary number to be displayed. The - PWR CHCK signal shuts the system down.

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