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Diagnostic Wrap of an SDLC Adapter With a Single DMA Channel

IP.com Disclosure Number: IPCOM000043358D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Nowell, JT: AUTHOR [+2]

Abstract

Diagnostic testing of a Synchronous Data Link Control (SDLC) Communication Adapter can be accomplished in both transit and receive operations with only one Direct Memory Access (DMA) channel. In a system with limited DMA resources, an SDLC communication adapter may have only one DMA channel available for both transmit and receive operations. This allows only half duplex operation and also poses a problem in testing the operation of the single DMA channel in diagnostic mode at rated speeds. The problem here is that wrapping transmit data to receive data does not fully test a single DMA channel since both memory read and memory write directions must be exercised.

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Diagnostic Wrap of an SDLC Adapter With a Single DMA Channel

Diagnostic testing of a Synchronous Data Link Control (SDLC) Communication Adapter can be accomplished in both transit and receive operations with only one Direct Memory Access (DMA) channel. In a system with limited DMA resources, an SDLC communication adapter may have only one DMA channel available for both transmit and receive operations. This allows only half duplex operation and also poses a problem in testing the operation of the single DMA channel in diagnostic mode at rated speeds. The problem here is that wrapping transmit data to receive data does not fully test a single DMA channel since both memory read and memory write directions must be exercised. Therefore, the wrapping must be done in two stages: 1) transmit DMA wrap, and 2) receive DMA wrap with the CPU either receiving or transmitting the other half of the operation, respectively. At speed at or above 1.0 megabit/second many processors merely cannot handle the data rate. Referring to the figures, this problem can be solved with the use of an SDLC adapter with buffered address and control bytes and implementation of the following two cases. In the circuit shown in Fig. 1, the transmit DMA wrap is done with a two-byte (address and control) operation with DMA supplying both transmit bytes and the adapter buffering two receive bytes until the main CPU is ready for them. Conversely, in the circuit shown in Fig. 2, the receive DMA requires t...