Browse Prior Art Database

Plastic Pin Array Package

IP.com Disclosure Number: IPCOM000043367D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Bourgeois, MP: AUTHOR [+2]

Abstract

This package combines the cost advantage of plastic molded dual in-line package (DIP) technology with the packaging density of ceramic pin arrays. Chip 2 is formed from a semiconductor wafer which is diced by partially cutting the wafer inwardly from its active surface with a wide kerf saw or the like. The individual chips are then removed from the wafer by breaking the uncut portions below the kerf surrounding each chip site in the wafer, thereby forming a peripheral flange F in the base of the chip 2, which is referred to as a wide kerf chip. The wide kerf chip 2 and the pins 3 are simultaneously molded into the plastic carrier 1 while concurrently forming the seal dam and standoff features 4 and 5, respectively, in the carrier 1. Flange F helps secure the chip 2 in the carrier 1.

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Plastic Pin Array Package

This package combines the cost advantage of plastic molded dual in-line package (DIP) technology with the packaging density of ceramic pin arrays. Chip 2 is formed from a semiconductor wafer which is diced by partially cutting the wafer inwardly from its active surface with a wide kerf saw or the like. The individual chips are then removed from the wafer by breaking the uncut portions below the kerf surrounding each chip site in the wafer, thereby forming a peripheral flange F in the base of the chip 2, which is referred to as a wide kerf chip. The wide kerf chip 2 and the pins 3 are simultaneously molded into the plastic carrier 1 while concurrently forming the seal dam and standoff features 4 and 5, respectively, in the carrier 1. Flange F helps secure the chip 2 in the carrier 1. After wirebonding the pin/chip interconnecting leads 6, a low viscosity droplet seal 7 is applied.

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