Browse Prior Art Database

Processor Shutdown Circuit

IP.com Disclosure Number: IPCOM000043370D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 24K

Publishing Venue

IBM

Related People

Dean, M: AUTHOR

Abstract

The Intel 80286 processor performs a shutdown cycle whenever an exception is detected while the processor is handling a previous exception. After a shutdown cycle the processor should be initialized by a reset input which remains active for sixteen system clock cycles. With the disclosed circuit, the reset does not affect the condition of I/O or memory devices in the system, thereby giving the system the capability of warning a user that a shutdown has occurred. A shutdown is indicated by the bus cycle status outputs, S0S1 and the A1 address output of the processor all going low with the memory/not I/O (MI0) output high. The low outputs enable AND gate 1 to clock the high M10 signal through a D-type flip-flop 2 to a second flip-flop 3.

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Processor Shutdown Circuit

The Intel 80286 processor performs a shutdown cycle whenever an exception is detected while the processor is handling a previous exception. After a shutdown cycle the processor should be initialized by a reset input which remains active for sixteen system clock cycles. With the disclosed circuit, the reset does not affect the condition of I/O or memory devices in the system, thereby giving the system the capability of warning a user that a shutdown has occurred. A shutdown is indicated by the bus cycle status outputs, S0S1 and the A1 address output of the processor all going low with the memory/not I/O (MI0) output high. The low outputs enable AND gate 1 to clock the high M10 signal through a D-type flip-flop 2 to a second flip-flop 3. Flip-flop 3 is clocked by a clock input CLK1 which is of a frequency 1/16th of the system clock. When this clock input goes high, the D input is passed to the Q output and then clocked through a further flip-flop 4 by CLK2, the system clock, to provide a reset output to the processor. The reset output clears flip-flop 2 which results in the termination of the reset signal sixteen system clocks later.

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