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16-Bit Data Transfer Using 8-Bit Direct-Memory Access Controller

IP.com Disclosure Number: IPCOM000043376D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Dean, M: AUTHOR [+2]

Abstract

An 8-bit DMA (Direct-Memory Access) controller is used to effect 16-bit data transfers between memory and I/O devices. The controller 1 is coupled conventionally to receive CPU hold acknowledge (HLDA), I/O DMA request (DRQ) and system data (SD) signals, and to provide hold request (HRQ), DMA acknowledge (DACK) and command signals, including I/O read and write, memory read and write, and ready commands. The address lines A0 through A7 are offset by one system bus address position so that A0 through A7 from the controller are connected to SA1 through SA8 of the system address. The address enable (AEN) output of controller 1 forces SA0 and the system bus high enable (BHE) to zero during all DMA cycles through inverting driver 2 and enabled drivers 3 and 4. This effectively multiplies the output address for a DMA cycle by two.

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16-Bit Data Transfer Using 8-Bit Direct-Memory Access Controller

An 8-bit DMA (Direct-Memory Access) controller is used to effect 16-bit data transfers between memory and I/O devices. The controller 1 is coupled conventionally to receive CPU hold acknowledge (HLDA), I/O DMA request (DRQ) and system data (SD) signals, and to provide hold request (HRQ), DMA acknowledge (DACK) and command signals, including I/O read and write, memory read and write, and ready commands. The address lines A0 through A7 are offset by one system bus address position so that A0 through A7 from the controller are connected to SA1 through SA8 of the system address. The address enable (AEN) output of controller 1 forces SA0 and the system bus high enable (BHE) to zero during all DMA cycles through inverting driver 2 and enabled drivers 3 and 4. This effectively multiplies the output address for a DMA cycle by two. A latch 5, which latches the high-order address lines from the system data bus, also provides a one-bit offset, so that SD0 through SD7 are coupled through latch 5 to system address lines SA9 through SA16. Latch 5 is enabled by the controller address enable output (AEN) and gated by the address strobe (ADSB). Since the address is multiplied by two external to controller 1, its base address register must be initialized with the desired memory address divided by two. Additionally, the base count register must be programmed with the number of byte transfers to be performed divided by...