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Memory Addressing Method for Reducing Double Bit Fails

IP.com Disclosure Number: IPCOM000043404D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Wortzman, D: AUTHOR

Abstract

By simply wiring the address bits for different chips in an ECC (error correcting code) word in different orders, so that wordline or bitline faults show up in different patterns from one chip location to another, the alignment of word line and bitline faults can be significantly reduced and the reliability of a memory array improved, without the addition of more hardware. With ECC the major types of double bit fails are: (a) chip with all other types, and (b) row with a column. Both of these categories, in conventional addressing schemes, have a probability of one of causing at least one double bit alignment when they occur. Also, in the conventional addressing scheme, a row and a row or a column and a column have a low probability N bits/chip of aligning.

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Memory Addressing Method for Reducing Double Bit Fails

By simply wiring the address bits for different chips in an ECC (error correcting code) word in different orders, so that wordline or bitline faults show up in different patterns from one chip location to another, the alignment of word line and bitline faults can be significantly reduced and the reliability of a memory array improved, without the addition of more hardware. With ECC the major types of double bit fails are: (a) chip with all other types, and (b) row with a column. Both of these categories, in conventional addressing schemes, have a probability of one of causing at least one double bit alignment when they occur. Also, in the conventional addressing scheme, a row and a row or a column and a column have a low probability N bits/chip of aligning. possible to reduce the probability of a row and a column aligning, at the expense of increasing the probability of two columns and two rows aligning, e.g., the overall probability of occurrence of double bit fails will considerably decrease. Consider the two 512 x 512-bit array chips shown in Fig. 1. a) Chip 1 is conventionally addressed, with bit 1 in the upper left-hand corner, and bit 512 in

the upper right-hand corner. Bit 513 is just

below bit 1, and bit 1024 is just below bit 412,

etc.

b) Chip 2 is addressed differently as follows: Bit 1

is in the upper left hand corner and bit 512 is in

the fourth row on the rightmost position of the

leftmost quarter of the chip.

c) Notice that...