Browse Prior Art Database

Clock Sequencing Circuit

IP.com Disclosure Number: IPCOM000043414D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Collins, JC: AUTHOR [+2]

Abstract

In a large data processor, a major control problem for the clocking system is properly sequencing the system clocks, i.e., starting and stopping the clocks in a prescribed relationship. The system clocks may be started and stopped during power up/down, maintenance and/or diagnostic procedures. Disclosed herein is a circuit for properly sequencing the clocks upon occurrence of a start or stop signal. The circuit uses two serially chained shift register latches for synchronizing the clocks. Fig. 1 illustrates the system latch, trigger and array clock timings during system operation (Fig. 1A), and the sequence for a stop command (Fig. 1B) and a start command (Fig. 1C). The problem is to guarantee the start and stop relationships of Figs. 1B and 1C, given the system operation of Fig. 1A.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 75% of the total text.

Page 1 of 2

Clock Sequencing Circuit

In a large data processor, a major control problem for the clocking system is properly sequencing the system clocks, i.e., starting and stopping the clocks in a prescribed relationship. The system clocks may be started and stopped during power up/down, maintenance and/or diagnostic procedures. Disclosed herein is a circuit for properly sequencing the clocks upon occurrence of a start or stop signal. The circuit uses two serially chained shift register latches for synchronizing the clocks. Fig. 1 illustrates the system latch, trigger and array clock timings during system operation (Fig. 1A), and the sequence for a stop command (Fig. 1B) and a start command (Fig. 1C). The problem is to guarantee the start and stop relationships of Figs. 1B and 1C, given the system operation of Fig. 1A. In general, two lines control the clock sequencing, one at the local level and one at the global level. The local line partitions the data processor into smaller maintenance elements, and this line is controlled synchronously. The global line controls the entire machine, and is asynchronous. The circuit of Fig. 2 accomplishes the required sequencing from either the asynchronous global or synchronous local control lines. Two shift register latches (SRLs) 1 and 2 synchronize the asynchronous global line to the system cycle time. A delay element 3 may be interposed between SRL 1 and SRL 2 to provide the proper synchronization. This synchronization prevents the g...