Browse Prior Art Database

New Salicide Spacer Technology

IP.com Disclosure Number: IPCOM000043424D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Iyer, S: AUTHOR [+2]

Abstract

In the fabrication of FETs using self-aligned silicide (salicide) techniques, metal silicide is formed over the gate as well as the source and drain regions; however, the gate should be electrically isolated from the source and drain regions by a break or opening in the metal silicide layer. In the prior art, silicon dioxide sidewalls over the gate are provided, and the metal on these sidewalls does not react to form silicide; only the metal over the polysilicon gate and the doped silicon source and drain regions reacts to form silicide. The prior art then provides techniques for selectively etching away the unreacted metal, leaving the silicon dioxide sidewalls as isolation between the non- etched silicide over the gate and source and drain regions.

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New Salicide Spacer Technology

In the fabrication of FETs using self-aligned silicide (salicide) techniques, metal silicide is formed over the gate as well as the source and drain regions; however, the gate should be electrically isolated from the source and drain regions by a break or opening in the metal silicide layer. In the prior art, silicon dioxide sidewalls over the gate are provided, and the metal on these sidewalls does not react to form silicide; only the metal over the polysilicon gate and the doped silicon source and drain regions reacts to form silicide. The prior art then provides techniques for selectively etching away the unreacted metal, leaving the silicon dioxide sidewalls as isolation between the non- etched silicide over the gate and source and drain regions. However, because the gate and source and drain regions are so closely spaced, slight traces of reacted metal on the silicon dioxide, isolation sidewalls may cause electrical shorting or bridging between the gate and source and drain regions. In an improved technique described herein, a very thin silicon dioxide sidewall is formed, and then a larger "spacer" formed of material which can be wet etched is placed over the sidewalls prior to metallization. Now, in addition to removing the unreacted metal, the spacer thereunder is also removed by a wet etch which does not attack the reacted silicide, thereby leaving a space between the gate and source and drain regions which contains silicon dioxide isolation material with no metal traces thereon. Fig. 1a shows a MOSFET device after the polysilicon gate 10 was delineated and a light ion implant in the source and drain areas 12 and 14, respectively. After a moderate oxidation wherein a thin SiO2 layer 16 was grown to cover the gate sidewall, a thick layer of spacer material 18 is...