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Emitter Butting Against Recessed Oxide Isolation in Bipolar Integrated Circuits

IP.com Disclosure Number: IPCOM000043428D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 3 page(s) / 67K

Publishing Venue

IBM

Related People

Jambotkar, CG: AUTHOR

Abstract

It is wellknown that if emitters can be butted against recessed oxide isolation (ROI) in bipolar transistors, appreciable improvement in device density and reduction in collector-base capacitance would result. Three different methods are described in this article to accomplish emitter butting. In the conventional processes, emitters cannot be butted against ROI without a high probability of creating either shorts or low punchthrough breakdown voltage between emitters and collectors. The reason for this is explained briefly with the help of Fig. A1-A3. Fig. A1 illustrates the essential NPN structure after base diffusion in a conventional process. Fig. A2 shows the structure after base reoxidation. This SiO2 must be removed for subsequent emitter diffusion.

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Emitter Butting Against Recessed Oxide Isolation in Bipolar Integrated Circuits

It is wellknown that if emitters can be butted against recessed oxide isolation (ROI) in bipolar transistors, appreciable improvement in device density and reduction in collector-base capacitance would result. Three different methods are described in this article to accomplish emitter butting. In the conventional processes, emitters cannot be butted against ROI without a high probability of creating either shorts or low punchthrough breakdown voltage between emitters and collectors. The reason for this is explained briefly with the help of Fig. A1-A3. Fig. A1 illustrates the essential NPN structure after base diffusion in a conventional process. Fig. A2 shows the structure after base reoxidation. This SiO2 must be removed for subsequent emitter diffusion. However, because of the wide process variability in the shape and thickness of the ROI "bird's beak," the position of the edge- defining emitter diffusion frequently turns out to be different than that of the edge which earlier defined the base.

As a consequence, the emitter depth near the ROI wall frequently either exceeds the base depth or approaches the same, as illustrated in Fig. A3. The three methods described below facilitate trouble-free emitter butting by arranging such that the emitter and the "intrinsic" portion of the base are defined by one and the same opening. The extrinsic base is formed independently. Method 1: 1.

In a conventional fashion, form the structure consisting of P- substrate 2, N subcollector 4, P

subisolation 6, N- epitaxial silicon 8, epi reox

SiO2 10, and ROI 12 (Fig. B1). 2. Using a suitable mask, etch SiO2 10 and deposit a layer of P-type doped oxide 14. Deposit

a layer of Si3N4 16 (Fig. B2). 3. Using a suitable mask, etch all contact windows in Si3N4 16. Then, using a block-out

mask, etch exposed oxide 14 in the emitter regions

(Fig. B3). 4. Introduce P and N dopants in the windows

formed in step 3 to form intrinsic bases and

emitters, respectively. Fig. B4

shows the structure following all heat cycling and

opening of...