Browse Prior Art Database

Programmed-Via Placement Pattern

IP.com Disclosure Number: IPCOM000043431D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

Linsker, R: AUTHOR

Abstract

In electronic device wiring packages presently using programmed-via sites around which wiring is deflected ('jogged'), the jogs increase wire length and can reduce yield by increasing the number of bendpoints. Such jogs can be eliminated by placing the via sites at different relative positions within different 'cells' of the wiring grid. An advantage is that the disclosed pattern avoids the reduced wirability that can result from other types of in-line via patterns. Consider an electronic wiring package with k wiring tracks per channel in both horizontal and vertical directions, where a channel is a horizontal or vertical swathe bounded by pins or other blockages, where a 'cell' is the rectangle defined by adjacent pins or blockages, and where to improve wirability one programmed-via (PV) is required per cell.

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Programmed-Via Placement Pattern

In electronic device wiring packages presently using programmed-via sites around which wiring is deflected ('jogged'), the jogs increase wire length and can reduce yield by increasing the number of bendpoints. Such jogs can be eliminated by placing the via sites at different relative positions within different 'cells' of the wiring grid. An advantage is that the disclosed pattern avoids the reduced wirability that can result from other types of in-line via patterns. Consider an electronic wiring package with k wiring tracks per channel in both horizontal and vertical directions, where a channel is a horizontal or vertical swathe bounded by pins or other blockages, where a 'cell' is the rectangle defined by adjacent pins or blockages, and where to improve wirability one programmed-via (PV) is required per cell. The PV site is often centered within the cell, and passing wires are deflected to either side of the PV site, as illustrated in Fig. 1. This 'jogging' allows a closer wire spacing than would be possible using straight wires. ('B' denotes a blockage or fixed via.) With in-line PV's, adequate via availability is achieved by placing potential PV sites at all grid positions within a cell, as shown in Fig. 2. (All x's denote potential PV sites. If B's are fixed vias, circled x's denote potential PV sites.) If vias are too large in diameter, however, one might be limited to one used via per cell. In either case, requiring an increased number of potential PV sites can increase fabrication cost. If an in-line via is allowed only at certain favored sites, as in Fig. 3, then a wire being routed to a via can obstruct neighboring tracks and the track containing the via will be obstructed at the via site, thereby impairing wirability. An improvement can be realized by defining several different types of cells, each with a different allowed via site, defining a supercell comprising several such cells, and repeating the supercell pattern across the grid, so that potential PV sites on any given wire track are evenly spaced. A supercell comprising two cells of each of two types,...