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Bit Substitution for Refresh of Systems With Unequal Memory and Bus Widths

IP.com Disclosure Number: IPCOM000043437D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

Livingston, DL: AUTHOR [+3]

Abstract

In dynamic-random access memories (DRAMs), a periodic refresh is necessary to prevent loss of data due to charge leakage of the dynamic storage cells. On modern DRAMs, this refresh is accomplished by delivering a row address strobe (RAS) to a fixed set of row addresses over a predetermined time period. In some computer systems, there is an inequality between the width of the memory subsystem and the width of the data block which is addressable by the system bus. This unequal memory/bus width station might arise, for example, in a system in which a high performance guest processor/memory combination is attached to a lower performance host system, in which case the width of the memory subsystem is greater than the width of the system bus.

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Bit Substitution for Refresh of Systems With Unequal Memory and Bus Widths

In dynamic-random access memories (DRAMs), a periodic refresh is necessary to prevent loss of data due to charge leakage of the dynamic storage cells. On modern DRAMs, this refresh is accomplished by delivering a row address strobe (RAS) to a fixed set of row addresses over a predetermined time period. In some computer systems, there is an inequality between the width of the memory subsystem and the width of the data block which is addressable by the system bus.

This unequal memory/bus width station might arise, for example, in a system in which a high performance guest processor/memory combination is attached to a lower performance host system, in which case the width of the memory subsystem is greater than the width of the system bus. This situation might also arise in a system in which an existing (narrow) memory subsystem is attached to an enhanced (widened) system bus, in which case the width of the memory subsystem is less than the width of the system bus. In order to reduce complexity and hence, save space, it is common practice to generate a series of row addresses for refresh purposes by means of a counter on the system board rather than to provide for refresh as part of the memory control logic. The output of the counter is multiplexed onto the low-order address lines of the system bus and delivered to the memory as a refresh request via a direct memory access (DMA) or equivalent means after every counter increment. A problem arises with mismatched memory/bus widths, in that the low-order address lines of the system bus are not routed directly to the DRAMs.

Instead, these low-order address lines of the system bus are shifted to the left or right before being sent to the address inputs of the DRAMs. As a result, the blind use of the specified refresh scheme means that only part of the DRAM bits would be refreshed. For purposes of a formal discussion of possible solutions to the problem of coupling unequal busses, let n = the width (in bytes) of the array in the memory

subsystem (a multiple of 2),

m = the width (in bytes) of the data block which is

addressable by the system (a multiple of 2),

(Note: m = n represents the trivial case, for which

case a solution is not increased.)

k = the number of bits in the refresh counter (the log

base 2 of the number of fixed row addresses needed for

refresh purposes), and

j = the number of bit positions which...