Browse Prior Art Database

Functional Failure Analysis and Diagnostic Model

IP.com Disclosure Number: IPCOM000043454D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Elias, AP: AUTHOR

Abstract

The functional failure analysis and diagnostic model disclosed here is used to predict the most probable failure mode (cause of semiconductor failure) in typical logic circuit arrangements. This is accomplished through the use of existing group A functional test results and power supply leakage measurements The model is based on the following items: o Characterization of chip design layout - masterslice design - personalization (metallurgy) design and layout o Existing functional diagnostic simulation o Power supply leakage measurements -these measurements indicate leakage type (interlevel shorts, resistive pipes, etc.), as well as location of such leakage in the chip under test. Examples: 1.

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Functional Failure Analysis and Diagnostic Model

The functional failure analysis and diagnostic model disclosed here is used to predict the most probable failure mode (cause of semiconductor failure) in typical logic circuit arrangements. This is accomplished through the use of existing group A functional test results and power supply leakage measurements The model is based on the following items: o Characterization of chip design layout

- masterslice design

- personalization (metallurgy) design and layout

o Existing functional diagnostic simulation

o Power supply leakage measurements

-these measurements indicate leakage type

(interlevel shorts, resistive pipes, etc.), as

well as location of such leakage in the chip under

test. Examples: 1. VEE - VCC (power supplies) - involves only external drivers and receivers. 2. VBB - VCC (power supplies) - involves only internal logic gates. These power supply leakage measurements will help determine if the fault is due to: 1. diffusion defect (resistive pipe) 2. level location of interlevel shorts With regard to the location of interlevel shorts between two levels of metallurgy, the exact location of such interlevel short can be inferred by combining the power supply leakage measurement results with the functional diagnostic simulation results. This is an advantage, since typically an interlevel short can occur between the first metallurgy level and the second metallurgy level or between the second metallurgy level and the...