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Synchronization of an Interprocessor Data Stream Through Alignment of Interprocessor Commands on a Byte Boundary

IP.com Disclosure Number: IPCOM000043455D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 1 page(s) / 13K

Publishing Venue

IBM

Related People

Johnson, RJ: AUTHOR [+2]

Abstract

Data exchange between two processors in serial communication can be disrupted if synchronization is dislocated due to interfering noise or other factors. This article presents a technique for effecting synchronization in such a situation by aligning the interprocessor commands on a byte boundary. Two processors communicating with each other via an interprocessor command stream will usually, at first, communicate properly when first powered up because they both start up on a known state. However, the processors may subsequently become misaligned on a byte or command boundary relative to each other due to a timeout error or noise corrupting the three interprocessor communication signals.

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Synchronization of an Interprocessor Data Stream Through Alignment of Interprocessor Commands on a Byte Boundary

Data exchange between two processors in serial communication can be disrupted if synchronization is dislocated due to interfering noise or other factors. This article presents a technique for effecting synchronization in such a situation by aligning the interprocessor commands on a byte boundary. Two processors communicating with each other via an interprocessor command stream will usually, at first, communicate properly when first powered up because they both start up on a known state. However, the processors may subsequently become misaligned on a byte or command boundary relative to each other due to a timeout error or noise corrupting the three interprocessor communication signals. A key problem in effecting necessary synchronization is to establish a byte and command boundary by means of a software RESET command rather than a power-on reset. The major advantage of a software-based reset is that recovery from all types of errors may be made by means of button depressions or host system commands. The solution, e.g., for a printer, involves a perception that, since the Selection processor is the master, or instigator of commands, its program must be cognizant of possible states the Escapement processor may be in. One possible state consists of Escapement looping while waiting to complete sending a byte to Selection. The Selection processor clears this state by toggling the DACK* signal 256 times. The SDATA signal is made low by Selection during this...