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Browse Prior Art Database

MC Substrate With Maximized Wiring Area

IP.com Disclosure Number: IPCOM000043465D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Darrow, RE: AUTHOR [+2]

Abstract

Apply a suitable layer of dielectric 1, i.e., polyimide, over the ceramic substrate 2 that has been previously pinned using pins 3 that are flush to the top of the ceramic. The dielectric 1 is etched to provide vias 4 to each I/O pin 3. Standard Cr-Cu-Cr 5 is then deposited, and the standard MC (metallized ceramic) process is completed. If the circuitry escape from under the IC chip is difficult or impossible using only one layer of circuitry, the initial circuitry could be standard MC with the lines from the C-4 pads going to via pads, away from the IC chip, on the top of the ceramic. Then, the polyimide could be applied and vias made to both the I/O pins and the via pads. The standard MC can now be used.

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MC Substrate With Maximized Wiring Area

Apply a suitable layer of dielectric 1, i.e., polyimide, over the ceramic substrate 2 that has been previously pinned using pins 3 that are flush to the top of the ceramic. The dielectric 1 is etched to provide vias 4 to each I/O pin 3. Standard Cr-Cu-Cr 5 is then deposited, and the standard MC (metallized ceramic) process is completed. If the circuitry escape from under the IC chip is difficult or impossible using only one layer of circuitry, the initial circuitry could be standard MC with the lines from the C-4 pads going to via pads, away from the IC chip, on the top of the ceramic. Then, the polyimide could be applied and vias made to both the I/O pins and the via pads. The standard MC can now be used.

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