Browse Prior Art Database

PARITY Checker/Generator

IP.com Disclosure Number: IPCOM000043467D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Torres, A: AUTHOR

Abstract

Parity checking of data in microprocessor storage channels typically requires a number of logic levels. The invention described in this article represents a method for generating a parity error signal for 36 bits utilizing only four logic levels and possibly only three logic levels (depending on polarity configuration). Parity Checking Requirements A major requirement imposed on the design of logic for microprocessor address and data channels is to check or generate parity on all four bytes of data plus the Tag logic, and to respond with the correct combination of ACK and NACK signals. This process typically requires a number of logic levels.

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PARITY Checker/Generator

Parity checking of data in microprocessor storage channels typically requires a number of logic levels. The invention described in this article represents a method for generating a parity error signal for 36 bits utilizing only four logic levels and possibly only three logic levels (depending on polarity configuration). Parity Checking Requirements A major requirement imposed on the design of logic for microprocessor address and data channels is to check or generate parity on all four bytes of data plus the Tag logic, and to respond with the correct combination of ACK and NACK signals. This process typically requires a number of logic levels. The following discussion, however, describes a method of checking parity for four bytes of data in just three or four levels of logic, depending on whether only one polarity, or both polarities, are available from the Data and Address latches. For the purposes of this description, it will be assumed that only one polarity is available from these latches. The method to be described is based on the generation of equations for the ODD and EVEN terms for three data bits. Preliminary Considerations Some background considerations are necessary before presentation of the invention itself. First, it is necessary to recognize that, for any three variables D1, D2, D3, the following two equations describe all the possible ODD combinations that can occur:

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Likewise, for any three variables D1, D2,...