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Mapping Circuit for Interlaced, All-Points-Addressable Display

IP.com Disclosure Number: IPCOM000043474D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 3 page(s) / 82K

Publishing Venue

IBM

Related People

St. Clair, JC: AUTHOR [+2]

Abstract

This special circuit maps a binary organized rectangular array bit map in an interlaced display on a raster scan CRT for all-points-addressable graphics. The circuit reads the addresses of the bit map, skipping every other scan line. This results in the display of odd and even fields without flickering. The mapping circuit operates essentially as a simple linear counter. Fig. 1 shows the mapping circuit 1 together with a multiplexer 2 that either allows the system to address a bit map 3 or allows the mapping circuit 1 to access the bit map 3. The data to be displayed are read out from bit map 3 via a shift register 4 to the video output. Timing logic 5 coordinates the necessary timing and synchronization signals fed to mapping circuit 1, multiplexer 2, bit map 3, shift register 4, and the CRT (not shown).

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Mapping Circuit for Interlaced, All-Points-Addressable Display

This special circuit maps a binary organized rectangular array bit map in an interlaced display on a raster scan CRT for all-points-addressable graphics. The circuit reads the addresses of the bit map, skipping every other scan line. This results in the display of odd and even fields without flickering. The mapping circuit operates essentially as a simple linear counter. Fig. 1 shows the mapping circuit 1 together with a multiplexer 2 that either allows the system to address a bit map 3 or allows the mapping circuit 1 to access the bit map 3. The data to be displayed are read out from bit map 3 via a shift register 4 to the video output. Timing logic 5 coordinates the necessary timing and synchronization signals fed to mapping circuit 1, multiplexer 2, bit map 3, shift register 4, and the CRT (not shown). Mapping circuit 1 consists of register 6, adder 7, and control logic 8. The register output holds the bit-map address. The register output is also fed back into one side of adder 7 so that adder 7 and register 6 combined form a counter. The other side of adder 7 is hard-wired to a constant value supplied by control logic 8. The value of this constant is equal to the number of bit-map memory accesses in a horizontal scan line, e.g., 40, considering the words in one line shown on the bit map of Fig. 2. Control logic 8 controls a single line which, when held active, supplies the constant to the adder input or, when held inactive, forces the adder input to zero. Control logic 8 also controls CLEAR and CLOCK inputs to register 6 and the CARRY input to adder 7. Operation of this circuit as an interleaved bit map is described as follows: As the CRT refresh beam sweeps horizontally across the tube, control logic 8 causes register 6 and adder 7 to act as a counter by holding the CARRY line to the adder active and clocking register
6. When the end of the horizontal scan line is reached, control circuit 8 deactivates the CARRY line, brings the ADD-CONSTANT signal to the adder 7 active, and supplies a CLOCK pulse to register 6. Since the value of the constant is equal to the number of bit-map memory accesses per horizontal scan, e.g., 40, the effect of this action is to advance the address register past the next scan line in the bit-map memory, i.e., from line 1 to 3 in Fig. 2. This is required to display a simple, two-dimensional array bit-map memory on an interleaved monitor. The process of displaying the scan lines from the even (odd) field and skipping over the scan lines from the odd (even) field is repeated until the last scan line of the field has been displayed. During the vertical retrace, if the odd field has just ended and the even field is to be displayed, the CLEAR signal to register 6 is used to reset the bit-ma...