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LOGIC Event Synchronizer for Data Communications Between Two Logical Functions Having Different CLOCK Frequencies

IP.com Disclosure Number: IPCOM000043476D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Dierks, MM: AUTHOR

Abstract

Data communications between two asynchronous logic functions, operating at different fundamental clock frequencies, must be synchronized for every data interchange. This article presents a logic event synchronizer, an expedient for providing synchronization for communications in such an asynchronous environment. The exchange of data between two asynchronous logic functions is impossible. Without synchronization of the data exchange between clocked logic, race conditions will occur and invalid data will be transmitted. One setting in which this problem was encountered was in an effort to achieve cost reduction through implementation of a custom logic chip module which reduced two logic cards into one card of half the area of the previous design.

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LOGIC Event Synchronizer for Data Communications Between Two Logical Functions Having Different CLOCK Frequencies

Data communications between two asynchronous logic functions, operating at different fundamental clock frequencies, must be synchronized for every data interchange. This article presents a logic event synchronizer, an expedient for providing synchronization for communications in such an asynchronous environment. The exchange of data between two asynchronous logic functions is impossible. Without synchronization of the data exchange between clocked logic, race conditions will occur and invalid data will be transmitted. One setting in which this problem was encountered was in an effort to achieve cost reduction through implementation of a custom logic chip module which reduced two logic cards into one card of half the area of the previous design. The module was designed without compromise to previous functions; however, its operation is extremely slow in comparison to other microprocessor technology currently available. The module operates at a clock frequency of 750 kHz, yet it must communicate with other microprocessors operating at cycle times of 3 MHz. Since typical data exchange handshaking is synchronous in nature and does not cross clock-logic boundaries of different frequencies, it was desirable to find a means of establishing synchronization without incurring any external logic. These objectives were achieved by the present concept. The concept involves a two- step approach requiring a minimum of information from the high-speed microprocessor to cause a predictable chain of events to occur in the low-speed logic for a concise data exchange. This expedient recognizes that a single event in one logic function may be utilized to synchronize requisite data exchange with another logic function. As established by this expedient, the qualifying event is decoded and clocked into the logic event synchronizer, which produces a synchronizing pulse, timed to the receiving logic's clock cycle. Fig. 1 depicts the implementation of the logic event synchronizer in a communications application. The faster microprocessor logic "A" is transmitting data to the slower logic function "B". This transmission of data from A to B is characterized by an event synchronous to A, called SYNC-A. The event SYNC-A transitions only once during one clock cycle of the A-CLOCKS, but will not transition on every A- CLOCK cycle. The A-CLOCKS may have a variable period based on the activities of microprocessor logic A. The fundamental relationships of the clocks are illustrated in Fig. 2. Synchronization begins with a positive...