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Virtual to Real Mapping for Scientific Arrays

IP.com Disclosure Number: IPCOM000043487D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Agarwal, RC: AUTHOR [+2]

Abstract

In various applications large data arrays often stream through the cache causing severe degradation of the cache miss ratio. This article describes a virtual to real mapping that reduces the miss ratio for an important class of algorithms. In a large array requiring multiple 4K pages of memory these pages are contiguous in virtual address space. However, after being mapped by the supervisor to real page frames, they may no longer be contiguous in memory. When subsequently mapped into the cache (this mapping is of the real address), the 4K pages may then overlap and interfere with one another, causing a high cache miss rate.

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Virtual to Real Mapping for Scientific Arrays

In various applications large data arrays often stream through the cache causing severe degradation of the cache miss ratio. This article describes a virtual to real mapping that reduces the miss ratio for an important class of algorithms. In a large array requiring multiple 4K pages of memory these pages are contiguous in virtual address space. However, after being mapped by the supervisor to real page frames, they may no longer be contiguous in memory. When subsequently mapped into the cache (this mapping is of the real address), the 4K pages may then overlap and interfere with one another, causing a high cache miss rate. A solution to this problem is for the supervisor to always map the virtual page address into a real page address, which is its equivalent modulo the number of pages in a single associate class of the cache. For example, if the cache is of size 32K, and is 4-way set associative, up to ((32K)/4K)/4=2 contiguous pages can reside in the cache without interfering with one another; in this case the real frame address should be equivalent to the virtual address modulo 2. A mapping such that the real page frame is equal to the virtual page address modulo 4 will guarantee data contiguity in the cache.

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