Browse Prior Art Database

Port Expander for a Microprocessor

IP.com Disclosure Number: IPCOM000043494D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Walls, EV: AUTHOR

Abstract

This article describes a method and apparatus for providing additional output ports on a microprocessor. The apparatus and method use the microprocessor address bus, latches, microprocessor write line and a generated control line. The configuration for the microprocessor with expanded port is shown in the figure. The microprocessor address bus is connected to a random-access memory (RAM) 10 and a plurality of latches identified by numerals 12, 14 and 16. A data bus 18 interconnects RAM 10 and latch 12. Similarly, the G terminal of latch 12 is tied to the microprocessor while the G terminals of latches 14 and 16 are connected to OR circuits 20 and 22, respectively. The write (WR) signal line of the microprocessor together with an A and B line are tied to positive OR gates 20 and 22 to generate a select signal on line 24.

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Port Expander for a Microprocessor

This article describes a method and apparatus for providing additional output ports on a microprocessor. The apparatus and method use the microprocessor address bus, latches, microprocessor write line and a generated control line. The configuration for the microprocessor with expanded port is shown in the figure. The microprocessor address bus is connected to a random-access memory (RAM) 10 and a plurality of latches identified by numerals 12, 14 and 16. A data bus 18 interconnects RAM 10 and latch 12. Similarly, the G terminal of latch 12 is tied to the microprocessor while the G terminals of latches 14 and 16 are connected to OR circuits 20 and 22, respectively. The write (WR) signal line of the microprocessor together with an A and B line are tied to positive OR gates 20 and 22 to generate a select signal on line 24. In this configuration the microprocessor's WR line is used to ensure correct data setup. Line 24 enables the microprocessor to select a particular latch. In operation, the microprocessor polls either the A or B line "low" and then writes to a dummy memory location. The net effect of this process enables the microprocessor to select a desired additional port.

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