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Demultiplexer Circuit for Testing Embedded Arrays

IP.com Disclosure Number: IPCOM000043515D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 81K

Publishing Venue

IBM

Related People

Omet, D: AUTHOR

Abstract

A random-access memory (RAM) embedded in a logic gate array chip and exhibiting a wide data-out bus, is surrounded by a demultiplexing circuit in order to test each data-out bit with a small number of fixed pads. As schematically shown in Fig. 1 the RAM is organized in such a way that each word is composed of 8 bytes, the 72 bits of which feed a random logic integrated on the same chip as the RAM. The function of the demultiplexing circuit is to provide a fixed and short path to test the array in order to measure accurately AC performance. In test mode, a 1-out-of-8 byte decoder is used; one of its output lines is at an UP level when the seven others are at a low level depending upon the input combination of byte address bits BY 0, 1, 2. Each one of these lines controls in parallel the 9 bits of a given byte.

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Demultiplexer Circuit for Testing Embedded Arrays

A random-access memory (RAM) embedded in a logic gate array chip and exhibiting a wide data-out bus, is surrounded by a demultiplexing circuit in order to test each data-out bit with a small number of fixed pads. As schematically shown in Fig. 1 the RAM is organized in such a way that each word is composed of 8 bytes, the 72 bits of which feed a random logic integrated on the same chip as the RAM. The function of the demultiplexing circuit is to provide a fixed and short path to test the array in order to measure accurately AC performance. In test mode, a 1-out-of-8 byte decoder is used; one of its output lines is at an UP level when the seven others are at a low level depending upon the input combination of byte address bits BY 0, 1, 2. Each one of these lines controls in parallel the 9 bits of a given byte. When this line is at an UP level, the nine RAM drivers (DVR) are enabled, and when it is at a down level, the data out are forced to the one state. Since all the same order bits are connected together through isolation gates and since this connection is an AND dot, only the enable byte will be accessible through the array test drivers (ATD). The test mode must be inhibited when the random logic communicates with the 72 bits of the RAM. In the system mode, the RAM enable signal is at an UP level. It is applied to the RAM drivers through a multiplexer (Fig. 2). The test control signal T is at an UP level in tes...