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Data Patterns for Bus or RAM Checkout

IP.com Disclosure Number: IPCOM000043517D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 4 page(s) / 48K

Publishing Venue

IBM

Related People

Haigh, DC: AUTHOR

Abstract

Data patterns are described which will provide an exhaustive checkout of a bus with a minimum number of patterns. These diagnostic patterns may also be used for random-access memory (RAM) checkout. The patterns are derived from an application of a well-known binary search technique and diagnostically check that each line can transmit both ones and zeros, that two or more of the lines are not interchanged and that two or more of the lines are not shorted together. In general, several steps are required: firstly with the bus divided into halves ones are transmitted on one half and zeros transmitted on the other half, then with each half halved again and successively halved until each has only one bit, and finally a check that all lines can transmit both ones and zeros. This method may be extended to check parity bits.

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Data Patterns for Bus or RAM Checkout

Data patterns are described which will provide an exhaustive checkout of a bus with a minimum number of patterns. These diagnostic patterns may also be used for random-access memory (RAM) checkout. The patterns are derived from an application of a well-known binary search technique and diagnostically check that each line can transmit both ones and zeros, that two or more of the lines are not interchanged and that two or more of the lines are not shorted together. In general, several steps are required: firstly with the bus divided into halves ones are transmitted on one half and zeros transmitted on the other half, then with each half halved again and successively halved until each has only one bit, and finally a check that all lines can transmit both ones and zeros. This method may be extended to check parity bits. A RAM is checked by considering it as a bus with one line for each bit and testing by successively dividing into halves, as previously. When pieces of equipment are interconnected by means of a parallel data bus, diagnostics are usually provided to verify the integrity of the bus.

The following technique allows all the above tests to be made with the minimum number of data patterns. Assume for the moment that the number of data bits in the bus is a power of 2. 1. Divide the bus into two halves and transmit ones on one half and zeros on the other half.

If the correct data is received, then it is known that

the two halves are independent, and that there can be

no shorts or interchanges between lines in different

halves. If any lines are shortened or interchanged,

such lines must be within the same half. 2. Imagine that each of these halves of the bus is a bus in its own right; test these 'imaginary' buses as

described in step 1 above. All of the 'imaginary'

buses may be tested simultaneously. The bus is then

successively split into halves until there is only 1

bit in each of all the 'imaginary' buses, and these

have been tested. Continue with step 3 below. 3. At this stage it is known that none of the bits of the bus are shortened and none are interchanged. It is

also known that all the bits except two of them can

transmit both ones and zeros; however, one of these two

bits will always have been a one and the other always a

zero.

It is therefore necessary to send and receive one final

pattern, in which these two bits are made to transmit

the inverse of the levels that they transmitted in the

previous patterns, in order to verify that they can

transmit both ones and zeros. If the number of bits in the bus is not a power of 2, the bus is mentally extended by as many bits as are needed to make the total number of bits a power of two, generating the patterns as described above, and then truncating the patterns down to the size of the actual bus by discarding the bits

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that were added.

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An example of the patterns that would be used to test a 16-bit bus is given...