Browse Prior Art Database

Active PMOS Load Circuit

IP.com Disclosure Number: IPCOM000043535D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Griffin, WR: AUTHOR [+2]

Abstract

The Active PMOS Load Circuit consists of an N channel combinatorial network 11; transistor TP1 whose gate is at ground and acts as the pull-up device; TP3 and TN3 acting as a CMOS buffer whose transfer (Vo vs. Vin) characteristics may be adjusted to provide early sensing of node N1 and feedback to TP2; TP2 which acts as a current booster raising the drive on node N1 assisting in pull up; and TP4 and TN4 which act as the final buffer (if necessary). During steady state, when N1 is low, TP1 is providing a DC current in order to start the pull-up action. TP2 is off since N2 is high. N1 rises (combinatorial network open), slowly at first, until buffer TP3/ TN3 goes low and turns on TP2. N1 reaches a full VH .

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Active PMOS Load Circuit

The Active PMOS Load Circuit consists of an N channel combinatorial network 11; transistor TP1 whose gate is at ground and acts as the pull-up device; TP3 and TN3 acting as a CMOS buffer whose transfer (Vo vs. Vin) characteristics may be adjusted to provide early sensing of node N1 and feedback to TP2; TP2 which acts as a current booster raising the drive on node N1 assisting in pull up; and TP4 and TN4 which act as the final buffer (if necessary). During steady state, when N1 is low, TP1 is providing a DC current in order to start the pull-up action. TP2 is off since N2 is high. N1 rises (combinatorial network open), slowly at first, until buffer TP3/ TN3 goes low and turns on TP2. N1 reaches a full VH .

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