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Fast Multiplier Accumulator/Subtractor Mechanism

IP.com Disclosure Number: IPCOM000043543D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Beraud, JP: AUTHOR

Abstract

The proposed mechanism allows a value to be added or subtracted from a multiplier output value as fast as possible. The multiplier circuit is made of N-1 parallel adders, N being the multiplier bit number, with carry propagation from stage to stage and a last fast adder stage with carry look-ahead propagation. To accumulate or substract a value from the multiplier output, instead of providing another fast adder at the multiplier output, a normal adder is arranged in the (N-1)th stage, which accumulates the new value with the partial result of the multiplication. An additional fast adder is provided in the Nth stage to accumulate the last partial product of the multiplication. Thus, the new value is added or subtracted before the completion of the multiplication.

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Fast Multiplier Accumulator/Subtractor Mechanism

The proposed mechanism allows a value to be added or subtracted from a multiplier output value as fast as possible. The multiplier circuit is made of N-1 parallel adders, N being the multiplier bit number, with carry propagation from stage to stage and a last fast adder stage with carry look-ahead propagation. To accumulate or substract a value from the multiplier output, instead of providing another fast adder at the multiplier output, a normal adder is arranged in the (N- 1)th stage, which accumulates the new value with the partial result of the multiplication. An additional fast adder is provided in the Nth stage to accumulate the last partial product of the multiplication. Thus, the new value is added or subtracted before the completion of the multiplication. The total gate number is reduced by the difference between the gate number required to design a stage to stage adder with carry propagation and the number of gates required to design a carry look-ahead propagation adder, which is significant.

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