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Wait State Test for Personal Computer Systems

IP.com Disclosure Number: IPCOM000043544D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Baker, RG: AUTHOR [+2]

Abstract

The illustrated circuit arrangement facilitates testing of certain functions in personal computer systems, particularly correct occurrences of processor "wait states" and various system timing clocks. The circuit may be incorporated into an integrated circuit card which connects to the system to be tested via the latter's I/O attachment sockets. After initialization by the system to be tested, which includes transfer to the testing circuit of an instruction specifying the number of "wait state" cycles to be expected for wait state tests, the subject circuit operates with minimal controlling intervention from the system to stimulate lines in the system interface bus and check resulting conditions via the bus.

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Wait State Test for Personal Computer Systems

The illustrated circuit arrangement facilitates testing of certain functions in personal computer systems, particularly correct occurrences of processor "wait states" and various system timing clocks. The circuit may be incorporated into an integrated circuit card which connects to the system to be tested via the latter's I/O attachment sockets. After initialization by the system to be tested, which includes transfer to the testing circuit of an instruction specifying the number of "wait state" cycles to be expected for wait state tests, the subject circuit operates with minimal controlling intervention from the system to stimulate lines in the system interface bus and check resulting conditions via the bus. Thereafter, on command from the system being tested, the circuit provides an input to the system indicative of the test results. Thus, with the system programmed to initialize this circuit, interrogate it for results and analyze the results, the tests can be made automatically and the results displayed without human intervention (in contrast to contemporary test techniques requiring action by a human technician to set up probes and manipulate external sensing equipment such as a logic analyzer or oscilloscope). Referring to the figure, interface chip A (e.g., an Intel 8255 programmable interface controlled by the system processor) initially checks its C port inputs PC0-PC3 to verify that corresponding outputs from "clock counter" B (e.g., one-half of a 74LS393 logic module) are all 0, a presettable condition and one that exists after resetting. For each test, the system processor programs into the chip A a 4-bit value to comparator C, through its B ports PB4-PB7, which will be compared to a 4-bit reference function presented to the comparator by oscillation counter D, as part of the timing test (e.g., the other half of the 74LS393 module). The purpose of this circuit is to present a "not ready" condition (I/O CH RDY going inactive or low), which for this system introduces additional processor cycles for a period of time to verify an appropriate response from the system processor. This period is programmable to stimulate the processor over a range of operation instead of a single value. The test is performed by counting the number o...