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Dynamic Address Buffer Without the Use of a Reference Voltage

IP.com Disclosure Number: IPCOM000043552D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Hanafi, HI: AUTHOR [+2]

Abstract

The address buffer circuit (Figs. 1 and 2) consists of two latches in series. The input latch consists of devices T2, T3, T4, T5, and T6. The output latch consists of devices T11, T12, T13, and T14. The input signal, ADD, is fed to the gate of device T5 in the input latch through transfer device T1, whose gate is clocked by d1 . In standby condition, d1 is high and d2 is low, enabling the state of the input latch to be controlled by the input signal. After CE goes low and the memory is activated, d1 goes low and the d2 clock goes high, latching the ADD signal statically into the input latch. At the same time, the latched information is passed to the output latch through two depletion-mode transfer devices T7 and T8 whose gates are clocked by d1 .

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Dynamic Address Buffer Without the Use of a Reference Voltage

The address buffer circuit (Figs. 1 and 2) consists of two latches in series. The input latch consists of devices T2, T3, T4, T5, and T6. The output latch consists of devices T11, T12, T13, and T14. The input signal, ADD, is fed to the gate of device T5 in the input latch through transfer device T1, whose gate is clocked by d1 . In standby condition, d1 is high and d2 is low, enabling the state of the input latch to be controlled by the input signal. After CE goes low and the memory is activated, d1 goes low and the d2 clock goes high, latching the ADD signal statically into the input latch. At the same time, the latched information is passed to the output latch through two depletion-mode transfer devices T7 and T8 whose gates are clocked by d1 . Also, as d2 rises, the information is latched dynamically in the output latch. Full VDD voltage is provided at the output nodes, AX and AX through bootstrap action between the drain and gate of devices T9 and T10.

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