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Differential Cascode Current Switch Logic for Adders With Fast Carry

IP.com Disclosure Number: IPCOM000043559D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Boudon, G: AUTHOR [+2]

Abstract

This article describes the embodiment of an adder with fast carry, integrated in a gate array of Differential Cascode Current Switch (DCCS) circuits. The silicon area, the delay and the dissipated power have been optimized by using the following logic functions to compute the sum Si and the Carry Ci of two bits Ai and Bi of the operands. (Image Omitted) The exclusive OR function (Ai + Bi) used in the computation of the carry allows the logic tree numbers to be reduced. Fig. 1 shows the logic implementation of a 4-bit adder of two operands A1, A2, A3, A4 and B1, B2, B3, B4; and Fig. 2 shows the specific DCCS circuit used in each stage. In this implementation six logic trees have been used and two elementary delays are needed.

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Differential Cascode Current Switch Logic for Adders With Fast Carry

This article describes the embodiment of an adder with fast carry, integrated in a gate array of Differential Cascode Current Switch (DCCS) circuits. The silicon area, the delay and the dissipated power have been optimized by using the following logic functions to compute the sum Si and the Carry Ci of two bits Ai and Bi of the operands.

(Image Omitted)

The exclusive OR function (Ai + Bi) used in the computation of the carry allows the logic tree numbers to be reduced. Fig. 1 shows the logic implementation of a 4-bit adder of two operands A1, A2, A3, A4 and B1, B2, B3, B4; and Fig. 2 shows the specific DCCS circuit used in each stage. In this implementation six logic trees have been used and two elementary delays are needed.

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