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Symmetry Test

IP.com Disclosure Number: IPCOM000043569D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Klein, W: AUTHOR [+4]

Abstract

A method is described for testing semiconductor memory chips. By means of this method, errors attributable to a slight asymmetry of the two half cells of a memory cell and errors attributable to other causes can be rapidly and reliably distinguished from each other. The figure is a detailed view of semiconductor chip cells arranged in the form of a matrix. This view shows twelve memory cells with two half cells each. In memory, the bit line pairs of each column are crossed twice to compensate for asymmetries of the bit-line capacitances. For layout reasons, two adjacent bit line pairs are mirrored. It is assumed that symmetry errors have occurred in the hatched half cells of the twelve illustrated memory cells, so that their read signal is weak compared with that supplied by the non-erroneous half cells.

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Symmetry Test

A method is described for testing semiconductor memory chips. By means of this method, errors attributable to a slight asymmetry of the two half cells of a memory cell and errors attributable to other causes can be rapidly and reliably distinguished from each other. The figure is a detailed view of semiconductor chip cells arranged in the form of a matrix. This view shows twelve memory cells with two half cells each. In memory, the bit line pairs of each column are crossed twice to compensate for asymmetries of the bit-line capacitances. For layout reasons, two adjacent bit line pairs are mirrored. It is assumed that symmetry errors have occurred in the hatched half cells of the twelve illustrated memory cells, so that their read signal is weak compared with that supplied by the non- erroneous half cells. For determining whether a memory cell is erroneous, a "0" is written into all memory cells connected to an even-numbered bit line pair BS0, BS2, etc., while a "1" is written into all memory cells connected to an odd- numbered bit line pair BS1, BS3, etc. When this information is subsequently read, only the memory cells, surrounded by solid lines, in rows II and III will prove erroneous. The symmetry error in rows I and IV will remain undetected, as the associated erroneous half cells supply a low read signal anyhow. In a second step, the information written into memory is reversed, i.e., a "1" is written into all memory cells connected to an even-n...