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Off-Chip Driver With Noise Reduction Circuit

IP.com Disclosure Number: IPCOM000043571D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Klein, W: AUTHOR [+3]

Abstract

An off-chip driver with an additional circuit is described. This circuit reduces the noise generated when the off-chip driver becomes conductive. The circuit diagram shows, in the lower part, a standard off-chip driver stage T1 and the logic circuits 2 used for its control. Also shown are the parasitic inductances LA and LG of the power supply lines, on which a noise voltage is produced in response to the current rise occurring when off-chip driver stage T1 becomes conductive. This noise voltage leads to a short drop of the supply voltage at node A, thus impairing the function of the logic circuits. To reduce the noise voltage, an additional circuit is provided which consists of resistor R1 and transistors T2 and T3, and is illustrated in the top part of the circuit diagram.

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Off-Chip Driver With Noise Reduction Circuit

An off-chip driver with an additional circuit is described. This circuit reduces the noise generated when the off-chip driver becomes conductive. The circuit diagram shows, in the lower part, a standard off-chip driver stage T1 and the logic circuits 2 used for its control. Also shown are the parasitic inductances LA and LG of the power supply lines, on which a noise voltage is produced in response to the current rise occurring when off-chip driver stage T1 becomes conductive. This noise voltage leads to a short drop of the supply voltage at node A, thus impairing the function of the logic circuits. To reduce the noise voltage, an additional circuit is provided which consists of resistor R1 and transistors T2 and T3, and is illustrated in the top part of the circuit diagram. Through line L1, the additional circuit is connected to a supply voltage VB which is higher than the supply voltage VA for the standard off-chip driver T1. The parasitic inductance of the supply line L1 is designated as LB. Transistor T2, wired as a diode, has its emitter connected to the node for applying the supply voltage VA and its collector, through resistor R1, to node VB for applying the higher supply voltage. The additional circuit is dimensioned so that in the standby state, with off-chip driver T1 being non-conductive, the current flow through transistors T2 and T3 is negligible. However, when off-chip driver T1 becomes conductive, the vo...