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Browse Prior Art Database

Storage Interface With BUFFER

IP.com Disclosure Number: IPCOM000043581D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 6 page(s) / 78K

Publishing Venue

IBM

Related People

Barsness, AR: AUTHOR [+7]

Abstract

One of the most important factors in the performance of a processor or CPU is the time required to access storage. If data cannot be obtained as fast as the processor logic can handle it, then a loss in the potential performance of the system will result. Many schemes have been devised to speed up storage accesses. One prior method used to improve the average access time of storage was to provide a 2-byte-wide data path between storage and the main storage processor (MSP). This technique of getting 2 bytes (or more) for each access is commonplace in the data processing industry. As in many systems throughout the computer industry, the present arrangement includes as part of its design the packaging of storage in increments so that storage can be supplied to users in different sizes.

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Storage Interface With BUFFER

One of the most important factors in the performance of a processor or CPU is the time required to access storage. If data cannot be obtained as fast as the processor logic can handle it, then a loss in the potential performance of the system will result. Many schemes have been devised to speed up storage accesses. One prior method used to improve the average access time of storage was to provide a 2-byte-wide data path between storage and the main storage processor (MSP). This technique of getting 2 bytes (or more) for each access is commonplace in the data processing industry. As in many systems throughout the computer industry, the present arrangement includes as part of its design the packaging of storage in increments so that storage can be supplied to users in different sizes. The increments are provided on cards containing 128K bytes. As is common practice in many systems, the address bits of lesser significance are supplied to all increments of storage (Fig. 1). The higher significant address bits (usually 2, 3 or 4 in number) are decoded, and a unique signal is provided from each decode to a specific increment of storage. This signal is referred to as a Card Select, and in this instance each Card Select addresses a 128K increment of storage. The decode of zero would select the address range of 0-128K; the decode of one would activate the second Card Select containing the address range from 128K- 256K; and so forth. Besides selecting a particular storage card, the Card Select signal conveys a timing parameter. The timing of address lines and the availability of valid data from the storage cards are normally specified as a function of the Card Select signal. The outputs of all storage cards are tied together on a common data bus going to the processor. The Card Select signal specifies which card can allow its data to be gated to the data bus. Another characteristic of many storages is that they require re freshing of the memory elements within the storage itself so that the electrical charge, denoting the one or zero state of the bit, does not decay through parasitic paths to the point of having an indistinguishable value. The 128K card is refreshed in 128 steps, each step refreshing 1K bytes. When each refresh step occurs, the storage is not available for normal data accesses. The 128K storage card is implemented as a 4-byte wide memory so that four consecutively addressed bytes are accessed at once. The next to the lowest significant address bit provided by the MSP is used on the storage card to actually gate out 2 bytes in parallel to the MSP. Since the access time is approximately 400 ns (100 ns set up and 300 ns storage access), it is sometimes worthwhile to save all four accessed bytes even though only two are actually sent to the MSP at any one time. For example, if a 6-byte instruction is being read from storage, at least 4 bytes can be accessed in only one 400 ns read. If the 4 bytes a...