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SBD With Controlled Leakage for CECL Delay Improvement

IP.com Disclosure Number: IPCOM000043590D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Bergeron, DL: AUTHOR [+2]

Abstract

Using ion-implantation to place an inert implant species at the semiconductor-metal interface will result in damage in the vicinity of the interface which has been determined to change the Schottky barrier diode's (SBD) forward and reverse characteristics. The following procedures detail method and structure for specific alterations of SBD reverse leakage characteristics. The process employs the use of argon implanted into silicon to high dose levels followed by a low temperature anneal (500-900ŒC) prior to the metallurgical evaporation. This results in increasing leakage with increasing dose and decreasing anneal temperature. More importantly, the leakage was much more controllable than the non-implanted or control samples.

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SBD With Controlled Leakage for CECL Delay Improvement

Using ion-implantation to place an inert implant species at the semiconductor- metal interface will result in damage in the vicinity of the interface which has been determined to change the Schottky barrier diode's (SBD) forward and reverse characteristics. The following procedures detail method and structure for specific alterations of SBD reverse leakage characteristics. The process employs the use of argon implanted into silicon to high dose levels followed by a low temperature anneal (500-900OEC) prior to the metallurgical evaporation. This results in increasing leakage with increasing dose and decreasing anneal temperature. More importantly, the leakage was much more controllable than the non-implanted or control samples. The controlled leakage of the implanted SBD can be used to significantly reduce the power performance product of multilevel emitter-coupled logic circuits. A common problem of circuits of this type is the definition of voltages on internal nodes that do not connect to either current sources or resistors. The drawing shows a 5-way AND in cascode- emitter coupled logic (CECL). Each input is separated by 1 Vbe (~.75 V at 25OEC). If junction leakages (~.100-.5 pa at 25OEC) are allowed to establish internal voltages, transitions of about .5 V occur at all but the first level. Placement of controlled leakage SBD (D1-D4) that provides 10-100 na into internal nodes reduces voltage transitions b...