Browse Prior Art Database

Fast Fourier Transform Calculating Circuit

IP.com Disclosure Number: IPCOM000043596D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 68K

Publishing Venue

IBM

Related People

Beraud, JP: AUTHOR [+2]

Abstract

The device shown in the drawings is to be used for calculating the Fourier transform generally used in digital signal processing. It is based on a multiplier accumulator unit (MAU) connected to a double output port data memory. Both are controlled by an engine able to generate the MAU control and random-access memory (RAM) addresses (Fig. 1). The MAU (Fig. 2), comprising three input registers RX, RY and RV, one multiplier, two accumulator subtracter circuits and eight output registers, allows the basic butterfly operation to be performed in four cycles.

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Fast Fourier Transform Calculating Circuit

The device shown in the drawings is to be used for calculating the Fourier transform generally used in digital signal processing. It is based on a multiplier accumulator unit (MAU) connected to a double output port data memory. Both are controlled by an engine able to generate the MAU control and random-access memory (RAM) addresses (Fig. 1). The MAU (Fig. 2), comprising three input registers RX, RY and RV, one multiplier, two accumulator subtracter circuits and eight output registers, allows the basic butterfly operation to be performed in four cycles. The butterfly operation combines two complex input points Xn and Xm and delivers two complex output points Xn' and Xm' according to the following expressions: Rn' = Rn + Rm cos r + Im sin r Rm' = Rn - Rm cos r - Im sin r

In' = In + Im cos r - Rm sin r

Im' = In - Im cos r + Rm sin r with R and I representing the real and imaginary parts of the input and output points. In the multiplier accumulator unit, one multiplication and two accumulations are performed in one cycle. The results are stored in two output registers. The load or /and the store operations of the data memory also require one cycle. The load/store cycle is overlapped with the computation (multiply-add) cycle. The sequencing of the four cycles is given in the following table which shows the calculations to be performed for two input point sets: Xn, Xm and XN and XM.

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