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High Speed Sense Scheme for a Bit-Organized Josephson Cache Memory

IP.com Disclosure Number: IPCOM000043611D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Beha, H: AUTHOR

Abstract

DC-powering a sense bus in a Josephson read-only memory permits a word-organized memory to appear externally as a bit-organized memory, considerably simplifying the sensing of a high-speed memory without incurring a speed penalty. In a bit-organized Josephson cache memory, a differentiating sense bus scheme is very demanding with respect to Imax tolerances and is occupying a very large area. In addition, due to the bit-organization of the memory array, the access time suffers due to the large amount of delay time T which is needed in order to avoid a sense-current "hangup." This additional delay time Tsy contributes a large amount (about 25%) to the total access time of the memory.

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High Speed Sense Scheme for a Bit-Organized Josephson Cache Memory

DC-powering a sense bus in a Josephson read-only memory permits a word- organized memory to appear externally as a bit-organized memory, considerably simplifying the sensing of a high-speed memory without incurring a speed penalty. In a bit-organized Josephson cache memory, a differentiating sense bus scheme is very demanding with respect to Imax tolerances and is occupying a very large area. In addition, due to the bit-organization of the memory array, the access time suffers due to the large amount of delay time T which is needed in order to avoid a sense-current "hangup." This additional delay time Tsy contributes a large amount (about 25%) to the total access time of the memory. This article describes a sense bus scheme for a Josephson memory which allows a word-organized memory array while appearing as a bit-organized cache memory chip to the external system. The sense bus scheme is shown in Fig. 1. The sense bus string is DC-powered. Due to the word-organized memory array with respect to the sense lines (S-lines), the sense-current hangup is avoided inherently, because the S-line currents can be established in the previous cycle. Therefore, the delay time Tsy is totally eliminated. In order to realize a bit- organized cache memory chip to the external system, the sense bus gates are controlled by the decoder output indicated by arrows from decoder D in Fig. 1. The sense bus gate is an asymme...