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High-Performance AND-OR Circuit

IP.com Disclosure Number: IPCOM000043634D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Beranger, H: AUTHOR [+2]

Abstract

The AND-OR circuit shown in the drawing presents an improved power x delay performance product and prevents an additional inverter stage from being used to recover the in-phase output of the logic gates. It comprises a current switch transistor arrangement T1,...,Tn followed by a push-pull stage. The current source of the current switch provides a current which is determined by a forward voltage VF of a Schottky barrier diode (SBD) across resistor R1. This source of current is switched off when at least one input of each group of inputs IN1 to INn is at "0". Due to this type of current source, the input threshold is equal to 2 VBE - VF, VBE being the base-emitter voltage of transistor T1.

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High-Performance AND-OR Circuit

The AND-OR circuit shown in the drawing presents an improved power x delay performance product and prevents an additional inverter stage from being used to recover the in-phase output of the logic gates. It comprises a current switch transistor arrangement T1,...,Tn followed by a push-pull stage. The current source of the current switch provides a current which is determined by a forward voltage VF of a Schottky barrier diode (SBD) across resistor R1. This source of current is switched off when at least one input of each group of inputs IN1 to INn is at "0". Due to this type of current source, the input threshold is equal to 2 VBE - VF, VBE being the base-emitter voltage of transistor T1. The common collectosr of T1, Tn are clamped for both states: the down level is limited by transistor TD and the up level is limited by transistors TP and TL. The swing is thus reduced so that a high operating speed is obtained. A highly capacitive load may be charged and discharged by means of the push-pull stage.

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