Browse Prior Art Database

Variable-Length Serializer

IP.com Disclosure Number: IPCOM000043638D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Cukier, M: AUTHOR

Abstract

The variable-length data serializer shown above may serialize words of up to 6 bits. An input register (A) includes six bit cells (i.e., a0 through a5). The outputs of the cells are fed into a first multiplexor (MPX1) under the control of a decoder (DECODE). The decoder is provided with five output lines, one for each possible serializer length. A second register (B) is also provided which includes six bit cells (i.e., b0 through b5). Also provided is a second multiplexer (MPX2). These circuits are connected as shown in the figure. Let us assume a three-bit word fed into a3, a4 and a5 is to be serialized as indicated by a MODE word. The MODE word is decoded which raises the DECODE 3-bit output line to the up logic level.

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Variable-Length Serializer

The variable-length data serializer shown above may serialize words of up to 6 bits. An input register (A) includes six bit cells (i.e., a0 through a5). The outputs of the cells are fed into a first multiplexor (MPX1) under the control of a decoder (DECODE). The decoder is provided with five output lines, one for each possible serializer length. A second register (B) is also provided which includes six bit cells (i.e., b0 through b5). Also provided is a second multiplexer (MPX2). These circuits are connected as shown in the figure. Let us assume a three-bit word fed into a3, a4 and a5 is to be serialized as indicated by a MODE word. The MODE word is decoded which raises the DECODE 3-bit output line to the up logic level. The multiplexer MPX1 is thus conditioned to transfer the a3 contents into b0, while a4 and a5 contents are being transferred into b4 and b5, respectively. At next clock (not shown) operation, the contents of b0 are fed to the serializer DATA OUTPUT while the b4 contents are fed to b0 (through MPX2) and the b5 contents are fed to b4. Finally, the last bit is transferred to b0 through MPX2 and, from there, to the DATA OUTPUT.

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